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参数资料
| 型号： | IRPT5051E |
| 厂商： | International Rectifier |
| 英文描述： | Integrated Power Stage for 15 hp Motor Drives |
| 中文描述： | 集成功率级驱动马达15马力 |
| 文件页数： | 12/12页 |
| 文件大小： | 440K |
| 代理商： | IRPT5051E |
IRPT5051
page 12
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS:
Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA:
7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY:
Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY:
Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST:
K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA:
315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/
Data and specifications subject to change without notice.
11/96
charged via the corresponding lower IGBT when this is switched
on.
Prior to initial application of the PWM input signals at start-
up, the bootstrap capacitors are uncharged. Thus, an upper IGBT
will not be turned on until after the corresponding lower IGBT
has first been turned on to charge the bootstrap capacitor for the
upper IGBT.
The minimum initial conduction period of each lower IGBT
at start-up should be about 50μsec, to allow sufficient time for
initial charging of the bootstrap capacitors.
In normal operation, the bootstrap capacitor maintains ad-
equate gate drive voltage for a period of 20 milliseconds.
The maximum duration of the PWM input pulses (1N1, 1N3
and 1N5) should not exceed this period.
Peak line-to-line fault current in excess of a nominal value of
65A and peak line-to-ground current in excess of 40A sets the
latch and internally inhibits the IGBT gate drive. The overcurrent
feedback signal, OI, simultaneously goes high. Reaction time to a
bolted short circuit is typically about 1μsec.
The LED1 lights up when any of the fault signals (UV, OI,
OT) set the latch, indicating a fault condition. When the RESET
signal is applied to the latch, the LED1 goes OFF if the fault that
is setting the latch clears.
The internal PWM inhibit condition is cleared by applying
15V signal to the RESET terminal for a minimum period of 1
microsecond.
Overtemperature Trip
If the temperature of the IMS substrate exceeds a nominal
value of 100°C, the overtemperature circuit sets the latch and in-
ternally inhibits the PWM input signals. The overtemperature
feedback signal, OT, simultaneously goes high.
The internal PWM inhibit condition is cleared by applying a
15V signal to the RESET terminal for a minimum period of 1
microsecond.
Heat Sink Requirements
Figures 5a through 5d (pp. 6-7) show the thermal resistance of
the heat sink required for various output power levels and PWM
switching frequencies. Maximum total losses of the unit are also
shown.
This data is based on the following key operating conditions:
G
The maximum continuous combined losses of the rectifier
and inverter occur at full pulse-width modulation. These
maximum losses set the maximum continuous operating
temperature of the heat sink.
G
The maximum combined losses of the rectifier and in-
verter at full pulse-width modulation under overload set
the incremental temperature rise of the heat sink during
overload.
G
The minimum output frequency at which full overload
current is to be delivered sets the peak IGBT junction
temperatures.
At low output frequency IGBT junction temperature tends to
follow the instantaneous fluctuations of the output current. Thus,
peak junction temperature rise increases as output frequency de-
creases.
Voltage Rise During Braking
The motor will feed energy back to the dc link during electri-
cal braking, forcing the dc bus voltage to rise above the level
defined by the input line voltage.
Deceleration of the motor must be controlled by appropriate
PWM control to keep the dc bus voltage within the rated maxi-
mum value of 850V.
An external dissipative braking circuit, which keeps the bus
voltage within the rated value, can be connected across the P and
N terminals if required.
J
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