参数资料
型号: IRS2158DSTRPBF
厂商: International Rectifier
文件页数: 22/30页
文件大小: 0K
描述: IC BALLAST CTRL 600V 16-SOIC
标准包装: 2,500
类型: 荧光灯驱动器
频率: 42.5 ~ 48.5 kHz
电流 - 电源: 3.5mA
电流 - 输出: 260mA
电源电压: 11.5 V ~ 15.6 V
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 带卷 (TR)
配用: IRPLDIM3-ND - KIT DES FLUOR BALLAST IRS2158D
IRS2158D(S)
When CPH exceeds 2/3*VCC (VCPHRUN+) for the second time, the IC enters run mode and the fault
counter becomes enabled. The ignition regulation is not active in run mode but the IC will enter fault mode
after 60 consecutive over-current faults and gate driver outputs HO and LO will be latched low.
Run Mode (RUN)
Once VCPH has exceeded 2/3*VCC for the second time (VCPHRUN), the IC enters run mode. CPH
continues to charge up to VCC. The operating frequency is at the minimum frequency (after the ignition
ramp) and is programmed by the external resistor (RMIN) at the FMIN pin. Should hard-switching occur at
the half-bridge at any time (open-filament, lamp removal, etc.), the voltage across the current sensing
resistor (RCS) will exceed the internal VCSTH+ threshold of 1.2 V and the fault counter will begin counting
(see Figure 5). Should the number of consecutive over-current faults exceed 60 (nEVENTS), the IC will
enter fault mode and the HO and LO gate driver outputs will be latched low. During run mode, the end-of-life
(EOL) window comparator and the DC bus under-voltage reset are both enabled.
Dimming
The application diagram shows how the operational amplifier can be configured with the ballast control pins
of the IRS2158 to realize a dimming ballast system, which regulates the lamp arc current. The opamp in this
IC is left uncommitted, so that the designer can utilize it in whatever way they require for the particular
application, for example it could be used to create a non-dimming ballast with regulated lamp power or a
more sophisticated end of lamp life detection circuit.
In this example the lamp arc current is compared with a DC control voltage to produce an error voltage that
steers the frequency by sinking current from the FMIN pin.
SD/EOL and CS Fault Mode
Should the voltage at the SD/EOL pin exceed 3 V or decrease below 1V (VEOLTH-) during run mode, an
end-of-life (EOL) fault condition has occurred. The end of life fault must remain for approximately 60 cycles
of LO before the IC enters fault mode. This is to prevent possible false tripping of the end of life shutdown
circuit caused by surges or transients at the AC line input. LO and HO gate driver outputs are all latched off
in the ‘low’ state. CPH is discharged to COM for resetting the preheat time and VCO is discharged to COM
for resetting the frequency. To exit fault mode, VCC can be decreased below VCCUV- (ballast power off) or
the SD pin can be increased above 5 V (VSDTH+) (lamp removal). Either of these will force the IC to enter
UVLO mode (see State Diagram, page 13). Once VCC is above VCCUV+ (ballast power on) and SD is
pulled above 5 V (VSDTH+) and back below 3 V (VSDTH-) (lamp re-insertion), the IC will enter preheat
mode and begin oscillating again.
The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has
been greater than 1.2 V (VCSTH+) for 60 (nEVENTS) consecutive cycles of LO. The voltage at the CS pin
is AND-ed with LO (see Figure 7) so it will work with pulses that occur during the LO on-time or DC. If the
over-current faults are not consecutive, then the internal fault counter will count down each cycle when there
is no fault. Should an over-current fault occur only for a few cycles and then not occur again, the counter will
eventually reset to zero. The over-current fault counter is enabled during preheat and run modes and
disabled during ignition mode.
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? 2009 International Rectifier
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