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| 型号： | IRS2530DSTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | IC DIMMING BALLAST CTRL 8-SOIC |
| 标准包装： | 1 |
| 系列： | DIM8™ |
| 类型： | 镇流器控制器 |
| 频率： | 34.2 ~ 115 kHz |
| 电流 - 电源： | 5mA |
| 电流 - 输出： | 260mA |
| 电源电压： | 12.6 V ~ 15.6 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 1383 (CN2011-ZH PDF) |
| 配用： | IRPLDIM5E-ND - KIT DES BALLAST 4LEVEL DIM FLUOR IRPLDIM4E-ND - KIT DES BALLAST 26W IRS2530D IRPLCFL8U-ND - KIT DES FLUOR BALLAST IRS2530D |
| 其它名称： | IRS2530DSTRPBFDKR |
IRS2530D(S)
Application Information and Additional Details
Information regarding the following topics is included as subsections within this section of the datasheet:
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UVLO Mode and IC Supply Circuitry
Preheat/Ignition (PH/IGN) Mode
Dim Mode
Non Zero-Voltage Switching (ZVS) Protection
Crest Factor Over-current Protection
Fault Mode and Lamp Reset
Component Selection
PCB Layout Guidelines
UVLO Mode and IC Supply Circuitry
The Under-Voltage Lock-Out Mode (UVLO) is defined as the state the IC is in when V CC is below the turn-on
threshold of the IC, V CCUV+ (12.5 V, typical), and LO is above the shutdown threshold, V LOSD+ (8.75 V, typical).
The UVLO circuit is designed to maintain an ultra-low supply current I QCCUV (<250 μ A), and to guarantee that
the IC is fully functional before the high- and low-side output gate drivers are activated. The VCC capacitor,
CVCC, is charged up from the DC bus voltage through supply resistors RVCC1 and RVCC2 (Figure 1). The
values of these resistors are chosen such that VCC reaches the UVLO+ turn-on threshold voltage at the
desired DC bus voltage level. Once the capacitor voltage on VCC reaches the start-up threshold, V CCUV+ , the
IC turns on and the HO and LO gate drive outputs start oscillating. The capacitor CVCC should be large
enough to hold the voltage at VCC above the V CCUV- threshold until the external auxiliary supply can take over
and supply the required voltage and current to the IC.
DCBUS(+)
RVCC1
RVCC2
DCP2
RLIM1
MHS
RLIM2
VCC
1
Bootstrap
FET
8
VB
RHO
CVCC1
DIM REF
and FB
CVCC2
CDIM
COM
DIM
VCO
2
3
4
Driver
15.6V
CLAMP
VCC
UVLO
High-
and
Low-
side
Driver
7
6
5
HO
VS
LO
CBS
RLO
CSNUB
TO LOAD
CVCO
MLS
CPH RVCO
DCP1
DCBUS(-)
LOAD RETURN
Figure 1, UVLO and supply circuitry.
An external charge pump circuit consisting of capacitor CSNUB and diodes DCP1 and DCP2, comprises the
auxiliary supply voltage for the low-side circuitry (Figure 1). To limit high peak currents that can flow from the
external charge pump to VCC, a zener diode (18 V, typical) should be used for the lower charge pump diode,
DCP1. Also, two low-ohmic resistors (RLIM1 and RLIM2, 10 ? each, typical) should be used together with
CVCC1 and CVCC2 to further limit and filter fast current spikes to minimize resulting voltage spikes that can
occur at VCC. An internal bootstrap MOSFET between VCC and VB and external supply capacitor, CBS,
determine the supply voltage for the high-side driver circuitry (Figure 1). The bootstrap MOSFET is turned on
when LO is ‘high’ and charges CBS from VCC each cycle to maintain the VB-to-VS voltage above the V BSUV-
threshold (8 V, typical). The value of CBS should be chosen such that the VB-to-VS voltage and ripple stays
above V BSUV- at all times. When VCC exceeds V CCUV+ for the first time, LO will first oscillate for several cycles
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