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| 型号： | IRU1050CD |
| 厂商： | International Rectifier |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 5A D-PAK |
| 标准包装： | 75 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 2.5 V ~ 3.3 V |
| 输入电压： | 最高 7V |
| 电压 - 压降（标准）： | 1.1V @ 5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 5A |
| 电流 - 限制（最小）： | 5.1A |
| 工作温度： | 0°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | D-Pak |
| 包装： | 管件 |
| 其它名称： | *IRU1050CD IRU1050-CD IRU1050-CD-ND |
IRU1050
2) The output capacitance is 5 3 1500 m F = 7500 m F
D t 3 D I 2 3 4.6
V ESR
V ESL
T
V C
D Vc =
Where:
= = 1.2mV
C 7500
D t = 2 m s is the regulator response time
LOAD
CURRENT
1050plt1-1.0
To set the output DC voltage, we need to select R1 and
R2:
LOAD CURRENT RISE TIME
3) Assuming R1=121 V , 0.1%:
Figure 5 - Typical regulator response
( V V -1 ) 3 R1 = ( 1.25 -1 ) 3 121 = 217.8 V
to the fast load current step.
An example of a regulator design to meet the Intel P54C ?
R2 =
REF
OUT 3.5
VRE specification is given below.
Assume the specification for the processor as shown in
Table 1:
Select R2=218 V , 0.1%
Selecting both R1 and R2 resistors to be 0.1% toler-
ance, results in the least amount of error introduced
Type of
Processor
Intel-P54C VRE
V OUT
Nominal
3.50 V
I MAX
4.6 A
Max Allowed
Output Tolerance
± 100 mV
by the resistor dividers leaving ≈ ± 1.3% error budget
for the IRU1050 reference which is within the initial
accuracy of the device.
Table 1 - Processor Specification
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is ≈ ± 53mV ( ± 1.5% of 3.5V
Finally, the input capacitor is selected as follows:
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the
main power supply response time is ≈ 50 m s, then
the minimum input capacitance for a 4.6A load step
is given by:
nominal), then the total step allowed for the ESR and
the ESL is ? 47mV.
C IN =
4.6 3 50
0.15
= 1530 m F
V DROP L Input voltage drop allowed in step 4
D I L Load current step
Assuming that the ESL drop is ? 10mV, the remain-
ing ESR step will be ? 37mV. Therefore the output
capacitor ESR must be:
37
ESR [ = 8m V
4.6
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500 m F, 6.3V has an ESR of less than 36m V typi-
The ESR should be less than:
(V IN - V OUT - D V - V DROP )
ESR =
D I
Where:
D V L Maximum regulator dropout voltage
cal. Selecting 5 of these capacitors in parallel has an
ESR of ≈ 7.2m V which achieves our design goal.
ESR =
(5 - 3.5 - 1.2 - 0.15)
4.6
= 0.032 V
The next step is to calculate the drop due to the ca-
pacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
Selecting two Sanyo 1500 m F, the same type as the
output capacitors, meets our requirements.
6
www.irf.com
Rev. 1.8
08/20/02
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| IRU1050CMTR | 功能描述:IC REG LDO ADJ 5A TO-263-3 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:1 系列:- 稳压器拓扑结构:正，固定式 输出电压:4V 输入电压:最高 16V 电压 - 压降（标准）:0.28V @ 150mA 稳压器数量:1 电流 - 输出:150mA 电流 - 限制（最小）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:5-VFBGA 供应商设备封装:5-uSMD 包装:Digi-Reel® 其它名称:LP2985AIBP-4.0DKR |
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