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参数资料
| 型号： | IRU1050CT |
| 厂商： | International Rectifier |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 5A TO-220-3 |
| 标准包装： | 80 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 2.5 V ~ 3.3 V |
| 输入电压： | 最高 7V |
| 电压 - 压降（标准）： | 1.1V @ 5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 5A |
| 电流 - 限制（最小）： | 5.1A |
| 工作温度： | 0°C ~ 150°C |
| 安装类型： | 通孔 |
| 封装/外壳： | TO-220-3 |
| 供应商设备封装： | TO-220AB |
| 包装： | 管件 |
| 产品目录页面： | 1384 (CN2011-ZH PDF) |
| 其它名称： | *IRU1050CT IRU1050-CT IRU1050-CT-ND |
IRU1050
Assuming the following specifications:
Air Flow (LFM)
V IN = 5V
0
100 200 300
400
V OUT = 3.5V
Thermalloy
6021PB
6021PB 6073PB
6109PB
7141D
I OUT(MAX) = 4.6A
AAVID
534202B 534202B 507302
575002 576802B
T A = 35 8 C
The steps for selecting a proper heat sink to keep the
junction temperature below 135 8 C is given as:
Note: For further information regarding the above com-
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
1) Calculate the maximum power dissipation using:
P D = I OUT 3 (V IN - V OUT )
AAVID.................PH# (603) 528 3400
Thermalloy...........PH# (214) 243-4321
P D = 4.6 3 (5 - 3.5) = 6.9W
Designing for Microprocessor Applications
2) Select a package from the regulator data sheet and
record its junction to case (or tab) thermal resistance.
Selecting TO-220 package gives us:
u JC = 2.7 8 C/W
3) Assuming that the heat sink is black anodized, cal-
culate the maximum heat sink temperature allowed:
Assume, u cs=0.05 ° C/W (heat-sink-to-case thermal
resistance for black anodized)
T S = T J - P D 3 ( u JC + u CS )
T S = 135 - 6.9 3 (27 + 0.05) = 116 8 C
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance ( u SA ) is calculated by first calculating the
temperature rise above the ambient as follows:
D T = T S - T A = 116 - 35 = 81 8 C
? T = Temperature Rise Above Ambient
As it was mentioned before, the IRU1050 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V sup-
ply. These processors demand a fast regulator that sup-
ports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitor is
imperative in the design of these regulator circuits.
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the ( D V ESR =ESR 3D I) and the ESL
= = 11.7 8 C/W
u SA =
D T
P D
81
6.9
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. ( D V ESL
=L 3D I/ D t). The output capacitance effect is a droop in
5) Next, a heat sink with lower u SA than the one calcu-
lated in Step 4 must be selected. One way to do this
is to simply look at the graphs of the “Heat Sink Temp
Rise Above the Ambient” vs. the “Power Dissipation”
and select a heat sink that results in lower tempera-
ture rise than the one calculated in previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current,
( D Vc= D t 3D I/C) where D t is the response time of the
regulator.
Rev. 1.8
08/20/02
www.irf.com
5
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