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参数资料
| 型号： | IRU1117CYTR |
| 厂商： | International Rectifier |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .8A SOT-223 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 2.5 V ~ 3.6 V |
| 输入电压： | 最高 7V |
| 电压 - 压降（标准）： | 1.2V @ 1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 800mA |
| 电流 - 限制（最小）： | 1.1A |
| 工作温度： | 0°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223 |
| 包装： | 带卷 (TR) |
IRU1117(PbF)
( V V -1 ) × R1 = ( 2.85 -1 ) × 121 = 154.8 ?
R2 =
Assuming the following specifications:
V IN = 5V
V F = 0.5V
V OUT = 2.85V
I OUT(MAX) = 0.8A
T A = 35 C
Where:
V F is the forward voltage drop of the D1 diode as
To set the output DC voltage, we need to select R1 and
R2:
4) Assuming R1 = 121 ? , 1%:
OUT
REF 1.25
Select R2 = 154 ? , 1%
shown in Figure 5.
5) Calculate the power dissapation for the schottky di-
+5V is significantly more than required to maintain drop-
out voltage across the IRU1117 when regulating V OUT to
2.85V. The "Extra" voltage means additional power is
dissapated in the IRU1117. The diode dissapates some
of this additional power, allowing the IRU1117 to run cooler.
ode (D1):
P D = V F × I OUT
P D = 0.5 × 0.8 = 0.4W
and select a suitable component.
The steps for selecting the right package with proper
board area for heat sinking to keep the junction tem-
perature below 135 C is given as:
5V
D1
C1
10uF
V IN
IRU1117
V OUT
2.85V
C2
22uF
1) Calculate the maximum power dissipation using:
P D = I OUT × (V IN - V F - V OUT )
P D = 0.8 × (5 - 0.5 - 2.85) = 1.32W
2) Calculate the maximum θ JA allowed for our ex-
Adj
R1
121
1%
R2
154
1%
θ JA(MAX) = = = 75.6 C/W
ample:
T J - T A 135 - 35
P D 1.32
3) Select a package from the data sheet with lower θ JA
than the one calculated in the previous step.
Selecting TO-252 (D-Pak) with at least 0.5" square
of 0.062" FR4 board using 1oz. copper has 70 ° C/W
which is lower than the calculated number.
Figure 5 - Final Schematic for half of the
GTL+ termination regulator.
Layout Consideration
The output capacitors must be located as close to the
V OUT terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the V OUT pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
www.irf.com
5
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