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参数资料
| 型号： | IRU3011CWTR |
| 厂商： | International Rectifier |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC CTRL SYNC BUCK 5BIT 20SOIC(W) |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel Pentium? III |
| 输入电压： | 5V，12V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC（宽型） |
| 包装： | 带卷 (TR) |
IRU3011
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two sets of output conditions that this regu-
lator must meet,
a) Vo=2.8V, Io=14.2A, D Vo=185mV, D Io=14.2A
b) Vo=2V, Io=14.2A, D Vo=140mV, D Io=14.2A
the regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total D Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
This intentional voltage level shifting during the load tran-
sient eases the requirement for the output capacitor ESR
at the cost of load regulation. One can show that the
new ESR requirement eases up by half the total trace
resistance. For example, if the ESR requirement of the
output capacitors without voltage level shifting must be
7m V then after level shifting the new ESR will only need
to be 8.5m V if the trace resistance is 5m V (7 + 5/2=9.5).
However, one must be careful that the combined “volt-
age level shifting” and the transient response is still within
the maximum tolerance of the Intel specification. To in-
sure this, the maximum trace resistance must be less
than:
Rs [ 2 3 (Vspec - 0.02 3 Vo - D Vo) / D I
Where :
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
ESR [
100
14.2
= 7m V
D Vo = Output ripple voltage
D I = load current step
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500 m F, 6.3V has an ESR of less than 36m V typical.
Selecting 6 of these capacitors in parallel has an ESR
of ≈ 6m V which achieves our low ESR goal.
Other type of electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the device is 5m V and if the total D I, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting.
For example, assuming:
Vspec = ± 140mV = ± 0.1V for 2V output
Vo = 2V
D Vo = assume 10mV = 0.01V
D I = 14.2A
Then the Rs is calculated to be:
Rs [ 2 3 (0.140 - 0.02 3 2 - 0.01) / 14.2 = 12.6m V
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6m V , the power dissipated is:
Io 2 3 Rs = 14.2 2 3 12.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5m V , then the power dissipated is about 1W
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7m V which translated to ≈ 6
of the 1500 m F, 6MV1500GX type Sanyo capacitors. With
Rs=5m V , the maximum ESR becomes 9.5m V which is
equivalent to ≈ 4 caps. Another important consideration
is that if a trace is being used to implement the resistor,
the power dissipated by the trace increases the case
temperature of the output capacitors which could seri-
ously effect the life time of the output capacitors.
8
www.irf.com
Rev. 1.6
08/20/02
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| IRU3012CWTR | 功能描述:IC REG BUCK SYNC 20SOIC(W) RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:20 系列:SIMPLE SWITCHER® 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:12V 输入电压:4 V ~ 60 V PWM 型:电压模式 频率 - 开关:52kHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 包装:管件 供应商设备封装:16-DIP 其它名称:*LM2575HVN-12LM2575HVN-12 |
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| IRU3013CQ | 制造商:IRF 制造商全称:International Rectifier 功能描述:VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER |
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