参数资料
型号: IRU3037CSTR
厂商: International Rectifier
文件页数: 10/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 220kHz
占空比: 95%
电源电压: 4.2 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
IRU3037/IRU3037A & (PbF)
6) Place second pole at the ESR zero.
F P2 = F ESR
Start to place the power components, make all the con-
nection in the top layer with wide, copper filled areas.
R 8 =
1
2 π × C 10 × F P2
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
Check if R 8 >
1
g m
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
× R 6
If R 8 is too small, increase R 7 and start from step 2.
7) Place second zero around the resonant frequency.
F Z2 = F LC
1
R 6 = - R 8
2 π × C 10 × F Z2
8) Use equation (1) to calculate R 5 .
V REF
R 5 =
V OUT - V REF
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
the ESR replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
Figure 8 shows a suggested layout for the critical com-
ponents, based on the schematic on page 14.
sient speed. The gain margin will be large enough to
PGnd
PGnd
provide high DC-regulation accuracy (typically -5dB to -
12dB). The phase margin should be greater than 45 ) for
Vin
C1
L1
C2A, B
PGnd
C7A, B
Vout
overall stability.
IC Quiescent Power Dissipation
8
7
6
5
L2
Power dissipation for IC controller is a function of ap-
plied voltage, gate driver loads and switching frequency.
The IC's maximum power dissipation occurs when the
1
2
Q1
3
4
IC operating with single 12V supply voltage (Vcc=12V
and Vc ? 24V) at 400KHz switching frequency and maxi-
mum gate loads.
D D D C
3 2 1 5
5
C4 6
U1
4
3
Single Point
Analog Gnd
Connect to
Power Ground plane
PGnd
IRU3037
Figures 9 and 10 show voltage vs. current, when the
gate drivers loaded with 470pF, 1150pF and 1540pF ca-
R4 C9 7
C8 8
2 C3
R5
1 R6
Analog Gnd
pacitors. The IC's power dissipation results to an exces-
sive temperature rise. This should be considered when
using IRU3037A for such application.
Analog Gnd
Figure 8 - Suggested layout.
(Topside shown only)
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
10
www.irf.com
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