参数资料
型号: IS15ABCP4EF
厂商: NKK Switches
文件页数: 3/4页
文件大小: 0K
描述: SMARTSWITCH STD YEL/GRN LED
应用说明: 36x24 LCD Appl Notes
产品变化通告: IS Series LCD Change 22/08/2011
RoHS指令信息: AT, IS Series, Cert of Compliance
3D 型号: IS15ABCP4EF
3D CAD Model Tutorial
标准包装: 1
系列: SmartSwitch™
类型: 按钮,LCD
样式: 标准
显示模式: 黄色,STN 正极
LED 颜色: 黄 - 绿,超亮
可视范围: 15.0mm L x 10.8mm W
外观尺寸: 23.13mm L x 20.59mm W
像素格式: 36 x 24
电路: SPST-NO
开关功能: 关-瞬时
触点额定电压: 0.1A @ 12VDC
电源电压: 4.5 ~ 5.5VDC
安装类型: 通孔
端接类型: PC 引脚
包装: 散装
工作温度: 0°C ~ 40°C
操作力: 2.2 牛顿
LED 正向电流: 15,15mA
LED 正向电压: 2.2,3.3VDC
行程范围: 1.8mm
配用: IS-INT DEM KIT-1-ND - SMARTSWITCH INT DEMONSTRATN KIT1
360-2326-ND - SMARTSWITCH DEVELOPMENT KIT 2
360-2322-ND - SMARTSWITCH DEMONSTRATION KIT 1
相关产品: 360-2428-ND - LOGIC BOARD FOR 36X24 LCD
360-2427-ND - CONTROL FOR 36X24 LCD PB/DISPLAY
360-2425-ND - SMARTSWITCH CONTROLLER LCD
IS-C1603-CONTROLLER-ND - CTLR FOR 16 STD SMART SWITCHES
AT548-ND - SMARTSWITCH HOUSING PANEL MOUNT
AT542-ND - SMARTSWITCH COUPLER
360-2437-ND - SWITCH ACC SOCKET
SMARTSWITCH
TM
BLOCK DIAGRAM & PIN CONFIGURATIONS
36 x 24 Dot Matrix
11
10
V LC
V DD
LCD Panel
seg1 seg36
5
7
FLM
SCP
Timing Control
Segment Driver
6
LP
CK
40bit Latch
8
Din
CK 40bit
D Shift RegisterQ
4
Dout
9
GND
SW
1
2
SW
12
BL-LED (+)
3
13
BL-LED (– )
BL-LED (– )
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
SW
SW
BL-LED (–)
Dout
FLM
LP
SCP
Din
GND
V DD
V LC
BL-LED (+)
BL-LED (–)
Name
Terminal of Switch
Terminal of Switch
Terminal of Backlight LED
Data Output
First Line Marker
Latch Pulse
Serial Clock Pulse
Data Input
Ground
Power
Power
Terminal of Backlight LED
Terminal of Backlight LED
Function
Normally open
Normally open
Cathode: Yellow
Display serial output. Can be used to connect to Din of the next SMARTSWITCH. As a result,
many SMARTSWITCHES can be controlled with one clock and data signal.
The marking signal for the first line data of LCD display. The first line of LCD will be selected
by the falling edge of LP signal during the high level (FLM).
Line data latch pulse will latch content of internal 40-bit shift register at falling edge for one
line of display. LP will also increment the display line by one.
Clock used by 40-bit internal shift register of the switch, shifting the display data bit presented
at Din at falling edge.
Display serial data bit. Note: to map the display data, because of the difference between the
number of internal shift register data (40) and the single line of LCD pixels (36), the first four
bits of data shifted will be dummy bits.
Power source for logic circuit
Power source for LCD drive
Anode for common
Cathode: green
NKK Switches ? email: smartswitch@nkkswitches.com ? Phone (480) 991-0942 ? Fax (480) 998-1435 ? www.nkksmartswitch.com
3
相关PDF资料
PDF描述
IS15ABCP4E SMARTSWITCH STD LED YELLOW
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IS15ABDP4EG SMARTSWITCH STD YELLOW/BLUE LED
IS15ABDP4E SMARTSWITCH STD BLUE W/YEL LED
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