参数资料
型号: IS41C44002AS(L)
英文描述: 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
中文描述: 4米× 4(16兆)动态与江户页面模式内存
文件页数: 6/20页
文件大小: 297K
代理商: IS41C44002AS(L)
6
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
5
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
V
IN
Vcc
Other inputs not under test = 0V
5
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V
V
OUT
Vcc
I
OH
=
5.0 mA with V
CC
=5V
I
OH
=
2.0 mA with V
CC
=3.3V
5
5
μA
V
OH
Output High Voltage Level
2.4
V
V
OL
Output Low Voltage Level
I
OL
= 4.2 mA with V
CC
=5V
I
OL
= 2 mA with V
CC
=3.3V
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
V
IH
5V
3.3V
2
2
mA
I
CC
2
Standby Current: CMOS
RAS
,
CAS
V
CC
0.2V
5V
3.3V
1
mA
0.5
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
CAS
,
Address Cycling, t
RC
= t
RC
(min.)
-50
-60
120
110
mA
I
CC
4
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
CAS
,
Cycling t
PC
= t
PC
(min.)
-50
-60
90
80
mA
I
CC
5
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
CAS
Cycling
t
RC
= t
RC
(min.)
-50
-60
120
110
mA
I
CC
S
Self Refresh current
(6)
Self Refresh Mode
5V,nromal version
5V, L version
3.3V, normal version
3.3, L version
500
350
450
350
μA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6. I
CCS
is for S version only.
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