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| 型号： | IS61LPS25672A |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 256 × 72，为512k × 36，1024K × 18 18MB的同步流水线，单周期取消选择静态RAM |
| 文件页数： | 14/34页 |
| 文件大小： | 229K |
| 代理商： | IS61LPS25672A |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
21
Rev. D
02/11/05
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
ISSI
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61LPS/VPSxxxxxx products have a serial boundary
scan Test Access Port (TAP) in the PBGA package only.
(The TQFP package not available.) This port operates in
accordance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (Vss) to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left disconnected. On power-up, the device will start in a
reset state which will not interfere with the device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
31 30 29
. . . 2 1 0
2
1
0
x
. . . . . 2 1 0
Bypass Register
Instruction Register
Identification Register
Boundary Scan Register*
TAP CONTROLLER
Selection Circuitry
TDO
TDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61LPS25672A-250B1 | 功能描述:静态随机存取存储器 18Mb 256Kx72 250MHz Sync 静态随机存取存储器 3.3v RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS25672A-250B1I | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS25672A-250B1L | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61LPS25672A-250B1-TR | 功能描述:静态随机存取存储器 18Mb 256Kx72 250MHz Sync 静态随机存取存储器 3.3v RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS51218A | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
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