参数资料
型号: IS61LPS51236A
厂商: Integrated Silicon Solution, Inc.
英文描述: 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
中文描述: 256 × 72,为512k × 36,1024K × 18 18MB的同步流水线,单周期取消选择静态RAM
文件页数: 4/34页
文件大小: 229K
代理商: IS61LPS51236A
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
ISSI
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Read
H
X
Read
H
L
H
Write Byte 1
H
L
H
Write All Bytes
H
L
Write All Bytes
L
X
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE
ADDRESS
CE
ADSP
ADSC
ADV
WRITE
OE
DQ
Deselected
None
H
X
L
X
High-Z
Read, Begin Burst
External
L
X
L
Q
Read, Begin Burst
External
L
X
H
High-Z
Write, Begin Burst
External
L
H
L
X
L
X
D
Read, Begin Burst
External
L
H
L
X
H
L
Q
Read, Begin Burst
External
L
H
L
X
H
High-Z
Read, Continue Burst
Next
X
H
L
H
L
Q
Read, Continue Burst
Next
X
H
L
H
High-Z
Read, Continue Burst
Next
H
X
H
L
H
L
Q
Read, Continue Burst
Next
H
X
H
L
H
High-Z
Write, Continue Burst
Next
X
H
L
X
D
Write, Continue Burst
Next
H
X
H
L
X
D
Read, Suspend Burst
Current
X
H
L
Q
Read, Suspend Burst
Current
X
H
High-Z
Read, Suspend Burst
Current
H
X
H
L
Q
Read, Suspend Burst
Current
H
X
H
High-Z
Write, Suspend Burst
Current
X
H
L
X
D
Write, Suspend Burst
Current
H
X
H
L
X
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3.
BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc.
BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf.
BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except
OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
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相关代理商/技术参数
参数描述
IS61LPS51236A-200B2 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51236A-200B2I 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51236A-200B2LI 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51236A-200B3 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,3.3v or 2.5v I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray
IS61LPS51236A-200B3I 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,512K x 36,200MHz,3.3v or 2.5v I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray