参数资料
型号: IS61LV25616-7T
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
中文描述: 256K X 16 STANDARD SRAM, 7 ns, PDSO44
封装: TSOP2-44
文件页数: 9/11页
文件大小: 94K
代理商: IS61LV25616-7T
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
09/29/00
1
2
3
4
5
6
7
8
9
10
11
12
IS61LV25616
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-7
-8
-10
-12
-15
Symbol
Parameter
Min. Max.
Unit
tWC
Write Cycle Time
7
8
10
12
15
ns
tSCE
CE to Write End
5
5.5
8
8
10
ns
tAW
Address Setup Time
5
5.5
8
8
10
ns
to Write End
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Setup Time
0
0
0
0
0
ns
tPWB
LB, UB Valid to End of Write
5
5.5
8
8
10
ns
tPWE1
WE Pulse Width
5
5.5
8
8
10
ns
tPWE2
WE Pulse Width (OE = LOW)
7
5
10
12
12
ns
tSD
Data Setup to Write End
3.5
4
6
6
7
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tHZWE(2)
WE LOW to High-Z Output
3
3.5
5
6
7ns
tLZWE(2)
WE HIGH to Low-Z Output
2
2
2
2
2
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Shaded area product in development
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IS61LV25616-8KI 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
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