参数资料
型号: IS61LV6424-9TQ
英文描述: 64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
中文描述: 64K的× 24 HIGH-SPEED的CMOS静态RAM为3.3V电源
文件页数: 7/10页
文件大小: 138K
代理商: IS61LV6424-9TQ
IS61LV6424
Integrated Circuit Solution Inc.
AHSR012-0D
S2-101
1
2
3
4
5
6
7
8
9
10
11
12
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-9
-10
-12
-15
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
9
10
12
15
ns
t
SCE
t
SCE
2
CE1
to Write End
CE2 to Write End
7
7
7
7
8
8
10
10
ns
t
AW
Address Setup Time
to Write End
7
7
8
10
ns
t
HA
Address Hold from Write End
0
0
0
0
ns
t
SA
Address Setup Time
0
0
0
0
ns
t
VS
V/
S
Setup Time
0
0
0
0
ns
t
PWE
1
WE
Pulse Width (
OE
= HIGH)
7
7
8
10
ns
t
PWE
2
WE
Pulse Width (
OE
= LOW)
9
10
12
15
ns
t
SD
Data Setup to Write End
5
5
6
7
ns
t
VW
V/
S
to Write End
7
7
8
10
ns
t
HD
Data Hold from Write End
0
0
0
0
ns
t
HZWE
(2)
WE
LOW to High-Z Output
4
5
6
7
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
3
3
3
3
ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
, LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
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