参数资料
型号: IS61LV6432-117TQI
英文描述: 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
中文描述: 64K的× 32 SYNCHRONOU拧管道静态RAM
文件页数: 12/16页
文件大小: 487K
代理商: IS61LV6432-117TQI
IS61LV6432
12
Integrated Circuit Solution Inc.
SSR005-0B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-166
-133
Min.Max.
-117
Min.Max.
-5
-6
-7
-8
Symbol
Parameter
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Unit
t
KC
Cycle Time
6
7.5
8.5
10
12
13
15
ns
t
KH
Clock High Time
2.4
2.8
3.0
3.5
4
6
6
ns
t
KL
Clock Low Time
2.4
2.8
3.0
3.5
4
6
6
ns
t
KQ
Clock Access Time
5
5
5
5
6
7
8
ns
t
KQX
(2)
Clock High to Output Invalid
1.5
1.5
1.5
1.5
1.5
2
2
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0
0
0
0
0
0
0
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
1.5
5
1.5
5
1.5
6
1.5
6
1.5
6
2
6
2
6
ns
t
OEQ
Output Enable to Output Valid
5
5
5
5
6
6
6
ns
t
OEQX
(2)
Output Disable to Output Invalid
0
0
0
0
0
0
0
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
0
0
0
0
0
0
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
3
3
4
4
5
6
6
ns
t
AS
Address Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
t
SS
Address Status Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
t
WS
Write Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
t
CES
Chip Enable Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
t
AH
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
t
SH
Address Status Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
t
WH
Write Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
t
CEH
Chip Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
t
CFG
Configuration Setup
(1)
2.5
30
35
35
45
52
60
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
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IS61LV6432-133PQ 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
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IS61LV6432-166TQ 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-5PQ 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM