参数资料
型号: IS61S6432
英文描述: 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
中文描述: 64K的× 32 SYNCHRONOU拧管道静态RAM
文件页数: 9/20页
文件大小: 523K
代理商: IS61S6432
IS61S6432
Integrated Circuit Solution Inc.
9
SSE003-0B
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
(Continued)
-5
-6
-7
-8
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max
Unit
t
KC
Cycle Time
10
12
13
15
ns
t
KH
Clock High Time
3.5
4
6
6
ns
t
KL
Clock Low Time
3.5
4
6
6
ns
t
KQ
Clock Access Time
5
6
7
8
ns
t
KQX
(1)
Clock High to Output Invalid
1.5
1.5
2
2
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
0
0
0
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
1.5
6
1.5
6
2
6
2
6
ns
t
OEQ
Output Enable to Output Valid
5
6
6
6
ns
t
OEQX
(1)
Output Disable to Output Invalid
0
0
0
0
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
0
0
0
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
4
5
6
6
ns
t
AS
Address Setup Time
2.5
2.5
2.5
2.5
ns
t
SS
Address Status Setup Time
2.5
2.5
2.5
2.5
ns
t
WS
Write Setup Time
2.5
2.5
2.5
2.5
ns
t
CES
Chip Enable Setup Time
2.5
2.5
2.5
2.5
ns
t
AVS
Address Advance Setup Time
2.5
2.5
2.5
2.5
ns
t
AH
Address Hold Time
0.5
0.5
0.5
0.5
ns
t
SH
Address Status Hold Time
0.5
0.5
0.5
0.5
ns
t
WH
Write Hold Time
0.5
0.5
0.5
0.5
ns
t
CEH
Chip Enable Hold Time
0.5
0.5
0.5
0.5
ns
t
AVH
Address Advance Hold Time
0.5
0.5
0.5
0.5
ns
t
CFG
(3)
Configuration Setup
35
45
66.7
80
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.
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