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参数资料
| 型号： | IS61SF6432 |
| 英文描述： | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 64K的× 32 SYNCHRONOU仛流，通过静态内存 |
| 文件页数： | 4/16页 |
| 文件大小： | 480K |
| 代理商： | IS61SF6432 |
IS61SF6432
4
Integrated Circuit Solution Inc.
SSR004-0B
TRUTH TABLE
ADDRESS
USED
OPERATION
CE1
CE2
CE3
ADSP ADSC
ADV WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
H
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
H
L
X
X
X
High-Z
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
L
Q
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
H
High-Z
Write Cycle, Begin Burst External
L
H
L
H
L
X
L
X
D
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
L
Q
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
D
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
L
Q
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
H
High-Z
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
L
Q
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
H
High-Z
Write Cycle, Suspend Burst Current
X
X
X
H
H
H
L
X
D
Write Cycle, Suspend Burst Current
H
X
X
X
H
H
L
X
D
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
4) and
BWE
are LOW or
GW
is
LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
FUNCTION
GW
BWE
BW1
BW2
BW3 BW4
READ
H
H
X
X
X
X
READ
H
X
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE All Bytes
X
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
相关PDF资料 |
PDF描述 |
|---|---|
| IS61SF6432-10PQ | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| IS61SF6432-10PQI | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61SF6432-10TQ | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61SF6432-10TQI | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| IS61SF6432-9PQ | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
| IS61SP12836-166B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-200B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464-100PQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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