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参数资料
| 型号： | IS61SP12836-5TQ |
| 英文描述： | x36 Fast Synchronous SRAM |
| 中文描述： | x36快速同步SRAM |
| 文件页数： | 9/16页 |
| 文件大小： | 108K |
| 代理商： | IS61SP12836-5TQ |
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
9
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
8
8.5
10
12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
(3)
Clock Frequency
—
100
—
90
—
66
—
66
MHz
t
KC
(3)
Cycle Time
10
—
11
—
15
—
15
—
ns
t
KH
Clock High Time
4
—
4.5
—
4.5
—
4.5
—
ns
t
KL
(3)
Clock Low Time
4
—
4.5
—
4.5
—
4.5
—
ns
t
KQ
(3)
Clock Access Time
—
8
—
8.5
—
10
—
12
ns
t
KQX
(1)
Clock High to Output Invalid
2
—
2
—
2
—
2
—
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
3.5
2
3.5
2
3.5
2
3.5
ns
t
OEQ
(3)
Output Enable to Output Valid
—
3.5
—
3.5
—
3.5
—
5
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
—
3.5
—
3.5
—
3.5
—
3.5
ns
t
AS
(3)
Address Setup Time
2
—
2
—
2
—
4
—
ns
t
SS
(3)
Address Status Setup Time
2
—
2
—
2
—
4
—
ns
t
WS
(3)
Write Setup Time
2
—
2
—
2
—
4
—
ns
t
CES
(3)
Chip Enable Setup Time
2
—
2
—
2
—
4
—
ns
t
AVS
(3)
Address Advance Setup Time
2
—
2
—
2
—
4
—
ns
t
AH
(3)
Address Hold Time
0.5
—
0.5
—
0.5
—
1.5
—
ns
t
SH
(3)
Address Status Hold Time
0.5
—
0.5
—
0.5
—
1.5
—
ns
t
WH
(3)
Write Hold Time
0.5
—
0.5
—
0.5
—
1.5
—
ns
t
CEH
(3)
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
1.5
—
ns
t
AVH
(3)
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
1.5
—
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
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