- 您现在的位置：买卖IC网 > PDF目录176102 > IS61SP25618-166B (INTEGRATED SILICON SOLUTION INC) Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85 PDF资料下载
参数资料
| 型号： | IS61SP25618-166B |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 256K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 1/15页 |
| 文件大小： | 120K |
| 代理商： | IS61SP25618-166B |
IS61SP25616
IS61SP25618
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V, +10%, -5% power supply
Power-down snooze mode
DESCRIPTION
The
ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with
ISSI's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by
BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
APRIL 2001
FAST ACCESS TIME
Symbol
Parameter
-166
-150
-133
-5
Units
tKQ
Clock Access Time
3.5
3.8
4
5
ns
tKC
Cycle Time
6
6.7
7.5
10
ns
Frequency
166
150
133
100
MHz
256K x 16, 256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
相关PDF资料 |
PDF描述 |
|---|---|
| IS61SP25618-166TQ | Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85 |
| IS61SP25618-5B | Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85 |
| IS61SP25618-5TQ | Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85 |
| IS61SP25618-5TQI | Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85 |
| IS61SPD25632T | Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61SP6464-100PQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464100TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464-100TQ | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 64K x 64 5ns 128-Pin TQFP |
| IS61SP6464-6TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61VF102418A-6.5B3 | 功能描述:静态随机存取存储器 18Mb,Flow-Through,Sync,1Mb x 18,6.5ns,2.5v I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。