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参数资料
| 型号： | IS82C59A-12X96 |
| 厂商： | Intersil |
| 文件页数： | 20/22页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR INTERRPT 12.5MHZ 28PLCC |
| 标准包装： | 750 |
| 控制器类型： | CMOS 优先中断控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 1mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 带卷 (TR) |
7
FN2784.5
March 17, 2006
These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
2. The 82C59A evaluates those requests in the priority
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
3. The CPU acknowledges the lNT and responds with an
INTA pulse.
4. Upon receiving an lNTA from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
6. These two INTA pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
The events occurring in an 80C86/88/286 system are the
same until step 4.
4. The 82C59A does not drive the data bus during the first
INTA pulse.
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I
/OR
I
/OW
INT
INTA
CASCADE
LINES
CAS 0
CAS 1
CAS 2
SP/EN
CS
RD
WR
INTA
INT
D7 - D0
A0
SLAVE PROGRAM/
ENABLE BUFFER
INTERRUPT
REQUESTS
82C59A
IRQ
7
6
5
4
3
2
1
0
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
D7
D6
D5
D4
D3
D2
D1
D0
Call Code
11
00
11
01
82C59A
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| IS82C59A-12Z96 | 功能描述:接口-I/O扩展器 W/ANNEAL PERIPH INT CNTRLR 5V 12 5MHZ RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
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