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参数资料
| 型号： | IS93C56A-3PI |
| 元件分类： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件页数： | 6/13页 |
| 文件大小： | 65K |
| 代理商： | IS93C56A-3PI |
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
11/12/02
IS93C46A
IS93C56A
IS93C66A
ISSI
PIN CONFIGURATIONS
8-Pin JEDEC SOIC “G”
8-Pin JEDEC SOIC “GR”
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
DIN
Serial Data Input
DOUT
Serial Data Output
ORG
Organization Select
NC
Not Connected
Vcc
Power
GND
Ground
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (6, 7, 8, or 9 bits), and data, if
appropriate. The clock signal may be held stable at
any moment to suspend the device at its last state.
This allows
clock-speed flexibility as well as
maximum power conservation.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a serial shift register. (Please
note that one logical “0” bit precedes the actual 8 or 16-bit
output data string.) The output on DOUT changes during the
low-to-high transitions of SK (see Figure 3).
Low Voltage Read
The IS93C46A/56A/66A have been designed to ensure that
data read operations are reliable in low voltage environ-
ments. They provide accurate operation with Vcc as low
as 2.5V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C46A/56A/66A has been designed to output a
continuous stream of memory content in response to a
single read operation instruction. To utilize this function, the
system asserts a read instruction specifying a start location
address. Once the 8 or16 bits of the addressed register have
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continu-
ously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Applications
The IS93C46A/56A/66A is very popular in many high-
volume applications which require low-power, low-
density storage. Applications using this device
include industrial controls, networking, and numerous
other consumer electronics.
Endurance and Data Retention
The IS93C46A/56A/66A is designed for applications re-
quiring up to 1M programming cycles (WRITE, WRALL,
ERASE and ERAL). It provides 40 years of secure data
retention without power after the execution of 1M program-
ming cycles.
Device Operations
The IS93C46A/56A/66A are controlled by a set of
instructions which are clocked-in serially on the Din pin.
Before each low-to-high transition of the clock (SK), the
CS pin must have already been raised to HIGH, and the
Din value must be stable at either LOW or HIGH. Each
1
2
3
4
8
7
6
5
CS
SK
DIN
DOUT
VDD
NC
ORG
GND
1
2
3
4
8
7
6
5
NC
VCC
CS
SK
ORG
GND
DOUT
DIN
1
2
3
4
8
7
6
5
CS
SK
DIN
DOUT
VCC
NC
ORG
GND
(Rotated)
8-Pin DIP, 8-Pin TSSOP
相关PDF资料 |
PDF描述 |
|---|---|
| IS93C56A-3ZI | EEPROM |
| IS93C56A-GRA | EEPROM |
| IS93C56A-PA | EEPROM |
| IS93C66 | |
| IS93C66A-3GI | EEPROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS93C56A-3PLA3 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-3ZI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| IS93C56A-3ZLA3 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-GRA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| IS93C56A-PA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
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