参数资料
型号: ISD4003-05MED
厂商: WINBOND ELECTRONICS CORP
元件分类: 音频合成
英文描述: 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封装: 8 X 13.40 MM, PLASTIC, TSOP1-28
文件页数: 14/37页
文件大小: 392K
代理商: ISD4003-05MED
21
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the
Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software con-
tains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before
the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 8-1 lists the typical programming time for
EEPROM access from the CPU.
Note:
1. 3.3 applies to the Atmel ATmega165A/ATmega165PA.
The following code examples show one assembly and one C function for writing to the EEPROM. To avoid that
interrupts will occur during execution of these functions, the examples assume that interrupts are controlled (e.g.
by disabling interrupts globally). The examples also assume that no Flash Boot Loader is present in the software. If
such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
Table 8-1.
EEPROM programming time.
Symbol
Number of calibrated
RC oscillator cycles
Typical programming time
EEPROM write (from CPU)
27 072
3.3/3.4ms (1)
相关PDF资料
PDF描述
ISD4003-05MEI 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
ISD4003-05MSI 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
ISD4003-06MED 360 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
ISD4003-06MEI 360 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
ISD4003-06MSI 360 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
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