参数资料
| 型号： | ISL12022MIBZR5421 |
| 厂商： | Intersil |
| 文件页数： | 8/31页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20SOIC |
| 应用说明： | Addressing Power Issues in Real Time Clock Appls |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 760 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，夏令时，闰年，SRAM |
| 存储容量： | 128B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
ISL12022MR5421
16
FN7576.3
June 7, 2012
enable and temperature conversion in progress bit.
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In this
mode, Alpha, Beta and ITRO registers are disabled and cannot be
accessed.
OSCILLATOR FAIL BIT (OSCF)
Oscillator Fail Bit indicates that the oscillator has failed. The
oscillator frequency is either zero or very far from the desired
32.768kHz due to failure, PC board contamination or mechanical
issues.
DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the
daylight saving time forward adjustment has happened. If a DST
Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit
will stay high when DSTFD event happens, and will be reset to “0”
when the DST Reverse event happens. It is read-only and cannot be
written. Setting time during a DST forward period will not set this bit
to “1”.
The DSTE bit must be enabled when the RTC time is more than
one hour before the DST Forward or DST Reverse event time
setting, or the DST event correction will not happen.
DSTADJ is reset to “0” upon power-up. It will reset to “0” when the
DSTE bit in Register 15h is set to “0” (DST disabled), but no time
adjustment will happen.
ALARM BIT (ALM)
This bit announces if the alarm matches the real time clock. If
there is a match, the respective bit is set to “1”. This bit can be
manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in the
SR can only set it to “0”, not “1”. An alarm bit that is set by an
alarm occurring during an SR read operation will remain set after
the read operation is complete.
LOW VDD INDICATOR BIT (LVDD)
This bit indicates when VDD has dropped below the pre-selected
trip level (Brownout Mode). The trip points for the brownout levels
are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in
PWR_ VDD registers. The LVDD detection is only enabled in VDD
mode and the detection happens in real time. The LVDD bit is set
whenever the VDD has dropped below the pre-selected trip level,
and self clears whenever the VDD is above the pre-selected trip
level.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the
PWR_VBAT registers. The LBAT85 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT85 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Example - When LBAT85 is Set To “1” In Battery Mode
The minute the register changes to 19h when the device is in
battery mode, the LBAT85 is set to “1” the next time the device
switches back to Normal Mode.
Example - When LBAT85 Remains at “0” In Battery Mode
If the device enters into battery mode after the minute register
reaches 20h and switches back to Normal Mode before the
minute register reaches 29h, then the LBAT85 bit will remain at
“0” the next time the device switches back to Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the
PWR_VBAT registers. The LBAT75 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT75 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Example - When LBAT75 is Set to “1” in Battery Mode
The minute register changes to 30h when the device is in battery
mode, the LBAT75 is set to “1” the next time the device switches
back to Normal Mode.
Example - When LBAT75 Remains at “0” in Battery Mode
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before minute
register reaches 50h, then the LBAT75 bit will remain at “0” the
next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022MR5421 internally)
when the device powers up after having lost all power (defined as
VDD = 0V and VBAT = 0V). The bit is set regardless of whether VDD
or VBAT is applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. The first valid write to the RTC section
after a complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
TABLE 2. STATUS REGISTER (SR)
ADDR
7
6
5
4
3
2
1
0
07h
BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF
相关PDF资料 |
PDF描述 |
|---|---|
| ISL12023IVZ | IC RTC/CLDR TEMP SNSR 14-TSSOP |
| ISL12024IRTCZ | IC RTC/CALENDER 64BIT 8-TDFN |
| ISL12024IVZ | IC RTC/CALENDAR EEPROM 8-TSSOP |
| ISL12025IVZ | IC RTC/CALENDAR EEPROM 8-TSSOP |
| ISL12026IBZ-T7A | IC RTC/CALENDAR EEPROM 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL12022MIBZ-T | 功能描述:实时时钟 REAL TIME CLK & TEMP COMPENSATED CRYSTAL RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| ISL12022MIBZ-T7A | 功能描述:IC RTC/CALENDAR TEMP SNSR 20SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| ISL12022MIBZ-TR5421 | 功能描述:实时时钟 REAL TIME CLK W/MFK IMPROVED ESD AIR RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| ISL12022MR5421 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated 5ppm |
| ISL12022M-R5421 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High-Accuracy RTC Modules, Feature-Rich RTCs |
发布紧急采购，3分钟左右您将得到回复。