参数资料
型号: ISL12057IBZ
厂商: Intersil
文件页数: 5/17页
文件大小: 0K
描述: IC RTC/CALENDAR I2C 8-SOIC
标准包装: 980
类型: 时钟/日历
特点: 警报器,闰年
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 1.8 V ~ 3.6 V
电压 - 电源,电池: 1.4 V ~ 1.8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
13
FN6755.1
March 3, 2011
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The seven MSBs are the device identifier.
These bits are “1101000”. Slave bits “1101” access the
register. Slave bits “000” specify the device select bits.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(see Figure 10).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12057 compares the device identifier and device
select bits with “1101000”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one-byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the internal
address counter is set to address 0h, so a current address
read of the RTC array starts at address 0h. When required,
as part of a random read, the master must supply the 1 Word
Address Bytes as shown in Figure 11.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101000x” in both places.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12057 responds with an ACK. At this point, the I2C
interface enters a standby state.
Read Operation
A Read operation consists of a 3- byte instruction followed
by one or more Data Bytes (see Figure 11). The master
device initiates the operation by issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL12057 responds with an ACK. Then,
the ISL12057 transmits Data Bytes, as long as the master
device responds with an ACK during the SCL cycle following
the eighth bit of each byte. The master device terminates the
read operation (issuing a STOP condition) following the last
bit of the last Data Byte (see Figure 11).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction. It
increments by one during transmission of each Data Byte.
After reaching the memory location 13h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
FIRST DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12057
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
000
ADDRESS
BYTE
A
C
K
LAST DATA
BYTE
A
C
K
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
SLAVE
ADDRESS BYTE
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
A6
A5
1
10
0
1
0
R/W
0
WORD ADDRESS
ISL12057
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