参数资料
| 型号： | ISL1208IB8Z-TKR5291 |
| 厂商： | Intersil |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC RTC LP BATT BACKED SRAM 8SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，SRAM |
| 存储容量： | 2B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
11
FN8085.8
September 12, 2008
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
TABLE 1. REGISTER MEMORY MAP
ADDR. SECTION
REG
NAME
BIT
RANGE
DEFAULT
7
654321
0
00h
RTC
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
0
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DT
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
00h
04h
MO
0
MO20
MO13
MO12
MO11
MO10
1 to 12
00h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
06h
DW
00000
DW2
DW1
DW0
0 to 6
00h
07h
Control
and
Status
SR
ARST
XTOSCB Reserved
WRTC
Reserved
ALM
BAT
RTCF
N/A
01h
08h
INT
IM
ALME
LPMODE
FOBATB
FO3
FO2
FO1
FO0
N/A
00h
09h
Reserved
N/A
00h
0Ah
ATR
BMATR1
BMATR0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
N/A
00h
0Bh
DTR
Reserved
DTR2
DTR1
DTR0
N/A
00h
0Ch
Alarm
SCA
ESCA
ASC22
ASC21
ASC20
ASC13
ASC12
ASC11
ASC10
00 to 59
00h
0Dh
MNA
EMNA
AMN22
AMN21
AMN20
AMN13
AMN12
AMN11
AMN10
00 to 59
00h
0Eh
HRA
EHRA
0
AHR21
AHR20
AHR13
AHR12
AHR11
AHR10
0 to 23
00h
0Fh
DTA
EDTA
0
ADT21
ADT20
ADT13
ADT12
ADT11
ADT10
1 to 31
00h
10h
MOA
EMOA
0
AMO20
AMO13
AMO12
AMO11
AMO10
1 to 12
00h
11h
DWA
EDWA
0000
ADW12
ADW11
ADW10
0 to 6
00h
12h
User
USR1
USR17
USR16
USR15
USR14
USR13
USR12
USR11
USR10
N/A
00h
13h
USR2
USR27
USR26
USR25
USR24
USR23
USR22
USR21
USR20
N/A
00h
ISL1208
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