参数资料
| 型号： | ISL1220IUZ |
| 厂商： | Intersil |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 98 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，SRAM |
| 存储容量： | 8B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
12
FN6315.0
June 22, 2006
NOTE: Writing to register 08h has restrictions. If VBAT>VDD, then no
byte writes to register 08h are allowed, only page writes beginning
with register 07h. If VDD>VBAT, then a byte write to register 08h IS
allowed, as well as page writes.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
frequency selection. If all bits are set to Zero, the FOUT
function is disabled.
FREQUENCY OUTPUT BIT (FOBATB)
This bit enables/disables the FOUT pin during battery backup
mode (i.e. VBAT power source active). When the FOBATB is
set to “1” the FOUT pin is disabled during battery backup
mode. This means the frequency output function is disabled.
When the FOBATB is cleared to “0”, the FOUT pin is enabled
during battery backup mode. The FOUT pin is open drain
output and requires a pull up resistor to VBAT for operation in
battery backup mode
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT -VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V.
(See Typical Performance Curves: IDD vs VCC with
LPMODE ON AND OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ pin when the RTC is triggered
by the alarm as defined by the alarm registers (0Ch to 11h).
When the IM bit is cleared to “0”, the alarm will operate in
standard mode, where the IRQ pin will be tied low until the
ALM status bit is cleared to “0”.
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
TABLE 4. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
000
32768
Hz
0
1
4096
Hz
0
1
0
1024
Hz
0
1
64
Hz
0
100
32
Hz
0
101
16
Hz
0
110
8
Hz
0
111
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
0
1/32
Hz
1
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
FIGURE 11. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
ISL1220
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