参数资料
型号: ISL21007DFB830Z-TK
厂商: Intersil
文件页数: 20/20页
文件大小: 0K
描述: IC VREF SERIES PREC 3V 8-SOIC
标准包装: 1
系列: FGA™
基准类型: 串联,精度
输出电压: 3V
容差: ±2%
温度系数: 10ppm/°C
输入电压: 3.2 V ~ 5.5 V
通道数: 1
电流 - 静态: 150µA
电流 - 输出: 7mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
产品目录页面: 1248 (CN2011-ZH PDF)
其它名称: ISL21007DFB830Z-TKDKR
ISL21007
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A "
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
AREA
4.00 (0.157)
5.80 (0.228)
0.50 (0.20)
0.25 (0.01)
x 45°
3.80 (0.150)
8 °
1
2
3
0.25 (0.010)
0.19 (0.008)
TOP VIEW
SIDE VIEW “B”
2.20 (0.087)
SEATING PLANE
1
8
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
2
7
0.60 (0.023)
1.27 (0.050)
-C-
3
4
6
5
1.27 (0.050)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
20
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6326.10
March 27, 2012
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