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参数资料
| 型号： | ISL22319 |
| 厂商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, I2C Bus, 128 Taps, Wiper Only(低噪声,低功率，I2C总线, 128抽头电位器) |
| 中文描述： | 低噪声，低功耗，I2C总线，128抽头，雨刷，只有（低噪声，低功率和I2C总线，128抽头电位器） |
| 文件页数： | 9/13页 |
| 文件大小： | 384K |
| 代理商： | ISL22319 |
9
FN6310.0
July 3, 2006
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
Serial Clock (SCL)
This is the serial clock input of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
Device Address (A1, A0)
The address inputs are used to set the least significant 2 bits
of the 7-bit I
2
C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22319. A maximum of 4 ISL22319 devices may occupy
the I
2
C serial bus.
Principles of Operation
The ISL22319 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I
2
C
serial interface providing direct communication between a
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to V
CC
and GND.
The RW pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the
DCP is controlled by an 7-bit volatile Wiper Register (WR).
When the WR of a DCP contains all zeroes (WR[6:0]= 00h),
its wiper terminal (RW) is closest to GND. When the WR
register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper
terminal (RW) is closest to V
CC
. As the value of the WR
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to GND
to the closest to V
CC
.
While the ISL22319 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between V
CC
and GND. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a non-
volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
I
2
C serial interface as described in the following sections.
Memory Description
The ISL22319 contains one non-volatile 8-bit register, known as
the Initial Value Register (IVR), and two volatile 8-bit registers,
Wiper Register (WR) and Access Control Register (ACR). The
memory map of ISL22319 is on Table 1. The non-volatile
register (IVR) at address 0, contains initial wiper position and
volatile register (WR) contains current wiper position.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically OR ‘d with SHDN pin. When this bit is 0,
DCP is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that
nonHvolatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
I
2
C Serial Interface
The ISL22319 supports an I
2
C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22319
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
—
ACR
1
Reserved
0
IVR
WR
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN
WIP
0
0
0
0
0
ISL22319
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