参数资料
型号: ISL22414TFU10Z-TK
厂商: Intersil
文件页数: 4/16页
文件大小: 0K
描述: IC POT DGTL 256TP LN LP 10-MSOP
标准包装: 1,000
系列: XDCP™
接片: 256
电阻(欧姆): 100k
电路数: 1
温度系数: 标准值 ±50 ppm/°C
存储器类型: 非易失
接口: 4 线 SPI(芯片选择)
电源电压: ±2.25 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 带卷 (TR)
12
FN6424.1
December 16, 2010
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).
The next byte sent to the ISL22414 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
Table 4 contains a valid instruction set for ISL22414.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are zero, then the read or write is to
either the IVR or the WR register (depends of VOL bit at
ACR). If the [R4:R0] are 10000, then the operation is on the
ACR.
Write Operation
A Write operation to the ISL22414 is a two or more bytes
operation. It requires first, the CS transition from HIGH to
LOW. Then host send a valid Instruction Byte, followed by
one or more Data Bytes to SDI pin. The host terminates the
write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write to
address 0, the MSB of the byte at address 10h (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16. Note, the internal non-volatile
write cycle starts with the rising edge of CS and requires up
to 20ms. During non-volatile write cycle the read operation to
ACR register is allowed to check WIP bit.
Read Operation
A Read operation to the ISL22414 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then
host send a valid Instruction Byte, followed by “dummy” Data
Byte, NOP Instruction Byte and another “dummy” Data Byte
to SDI pin. The SPI host receives the Instruction Byte
(instruction code + register address) and requested Data
Byte from SDO pin on the rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS pin from LOW to HIGH (see
Figure 17). Reading from the IVR will not change the WR, if
its contents are different.
BIT #
76
54
32
1
0
I2
I1
I0
R4
R3
R2
R1
R0
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
OPERATION
I2
I1
I0
R4
R3
R2
R1
R0
0
XXXX
X
NOP
0
1
XXXX
X
ACR READ
0
1
XXXX
X
ACR WRITE
1
0
R4
R3
R2
R1
R0
WR, IVR, GP or ACR READ
1
0
R4
R3
R2
R1
R0
WR, IVR, GP or ACR WRITE
where X means “do not care”
FIGURE 16. TWO BYTE WRITE SEQUENCE
CS
SCK
SDI
SDO
WR INSTRUCTION
DATA BYTE
1
3
4
5
7
8
9
10
11
12
13
14
15
16
26
ADDR
ISL22414
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