参数资料
型号: ISL23325UFVZ
厂商: Intersil
文件页数: 8/20页
文件大小: 0K
描述: IC DGTL POT 256POS 50K 14TSSOP
标准包装: 960
系列: XDCP™
接片: 256
电阻(欧姆): 50k
电路数: 2
温度系数: 标准值 65 ppm/°C
存储器类型: 易失
接口: I²C,2 线串口
电源电压: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
ISL23325
16
FN7870.0
June 21, 2011
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23325 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and the
device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23325 responds
with an ACK; then the ISL23325 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
10
1
00
A
C
K
WRITE
SIGNAL AT SDA
00 0
A0
A1
FIGURE 29. BYTE WRITE SEQUENCE
A2
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
10
1
00
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
00 0
A0
A1
A0
A1
FIGURE 30. READ SEQUENCE
A
C
K
A2
10 1 0
READ
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