参数资料
型号: ISL24212IRTZ
厂商: Intersil
文件页数: 5/12页
文件大小: 0K
描述: IC PROG 8BIT VCOM CALIBRTR 10TDF
标准包装: 100
类型: 校准器
应用: LCD 驱动器,基准电压发生器
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
供应商设备封装: 10-TDFN(3x3)
包装: 管件
ISL24212
2
FN7590.0
March 15, 2011
Block Diagram
Pin Configuration
ISL24212
(10 LD TDFN)
TOP VIEW
FIGURE 2. BLOCK DIAGRAM OF THE ISL24212
GND
DIGITAL
INTERFACE
DAC
REGISTERS
8-Bit EEPROM
CTL
DNC
CE
AVDD
SET
10
9
3
7
8
5
CS
DVR_OUT
2
1
Q1
A1
VCOM_OUT
INN
ANALOG DCP
AND
CURRENT SINK
VCOM BUFFER
AMPLIFER
A2
UP/DOWN
COUNTER
6
VDD
4
(*CONNECT THERMAL PAD TO GND)
INN
DVR_OUT
AVDD
1
2
3
4
10
9
8
7
VCOM_OUT
SET
CE
CTL
EXPOSED
THERMAL
PAD*
6 VDD
GND 5
DNC
Pin Descriptions
PIN
NAME
PIN
NUMBER
FUNCTION
INN
1
Negative input of the op amp. To create a unity-gain VCOM voltage buffer, connect this pin to the VCOM_OUT pin.
DVR_OUT
2
Current Sink Output. The sink current into the DVR_OUT (Digital Variable Resistor) pin is equal to the DAC setting times the maximum
adjustable sink current divided by 256. See the “SET” pin function description (pin 9) for setting the maximum adjustable sink
current.
AVDD
3
High-Voltage Analog Supply. Bypass to GND with 0.1F capacitor.
DNC
4
Do Not Connect to external circuitry. It is acceptable to ground this pin.
GND
5
Ground connection.
VDD
6
Digital power supply input. Bypass to GND with 0.1F capacitor.
CTL
7
Up/Down Control for internal counter and Internal EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter, adding 1 to the DAC setting, increasing the DVR_OUT sink current, and
lowering the divider voltage at the DVR_OUT pin.
A high-to-mid transition decrements the 8-bit counter, subtracting 1 from the DAC setting, decreasing the DVR_OUT sink current,
and increasing the divider voltage at the DVR_OUT pin.
To program the EEPROM, take this pin to >4.9V (see “CTL EEPROM Programming Signal Time” in the “Electrical Specification”
table on page 5 for details). Float when not in use.
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