参数资料
| 型号： | ISL28107FUZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 11/31页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP GP 1MHZ LN 8MSOP |
| 标准包装： | 1,500 |
| 放大器类型： | 通用 |
| 电路数： | 1 |
| 转换速率： | 0.32 V/µs |
| 增益带宽积： | 1MHz |
| 电流 - 输入偏压： | 15pA |
| 电压 - 输入偏移： | 5µV |
| 电流 - 电源： | 210µA |
| 电流 - 输出 / 通道： | 40mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 40 V，±2.25 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
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ISL28107, ISL28207, ISL28407
19
FN6631.7
February 25, 2013
Applications Information
Functional Description
The ISL28107, ISL28207 and ISL28407 are single, dual and
quad, very low 1/f noise (14nV/
√Hz @ 10Hz) precision op-amps.
These amplifiers feature very high open loop gain (50kV/mV) for
excellent CMRR (145dB) and gain accuracy. Both devices are
fabricated in a new precision 40V complementary bipolar DI
process.
The super-beta NPN input stage with bias current cancellation
provides bipolar-like levels of AC performance, with the low input
bias currents approaching JFET levels. The temperature
stabilization provided by bias current cancellation removes the
high input bias current temperature coefficient commonly found
variation over temperature.
The input offset voltage (VOS) has a very low, worst case value of
shows VOS as a function of supply voltage and temperature with
the common mode voltage at 0V for split supply operation.
The complementary bipolar output stage maintains stability
driving large capacitive loads (to 10nF) without external
compensation. The small signal overshoot vs. load capacitance is
shown in Figure 54.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). Both DC and AC performance remain virtually
unchanged over the complete 4.5V to 40V operating voltage
range. Parameter variation with operating voltage is shown in the
“Typical Performance Curves” beginning on page 11. The input
common mode voltage range sensitivity to temperature is shown
in Figure 38 (±15V).
Input ESD Diode Protection
The input terminals (IN+ and IN-) each have internal ESD
protection diodes to the positive and negative supply rails, a series
connected 500
Ω current limiting resistor followed by an
anti-parallel diode pair across the input NPN transistors (Circuit 1
FIGURE 51. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V,
±15V, ±20V
FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS =±15V
FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS =
±15V
FIGURE 54. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
Typical Performance Curves V
S = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise specified. (Continued)
TIME (s)
SMALL
SIGNAL
(V)
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0
5
10
15
20
25
30
35
40
RL = 2k, 10k
AV = 1
CL = 4pF
VOUT = 100mVP-P
VS = ±5V, ±15V, ±20V
TIME (s)
OUT
P
UT
(V)
INP
U
T
(
V
)
-0.06
-0.02
0.02
0.06
0.10
0.14
0.18
0.22
0.26
0
20
40
60
80
100 120 140 160 180 200
-1
1
3
5
7
9
11
13
15
INPUT
OUTPUT
VS = ±15V
RL = 10k
AV = 100
CL = 4pF
Rf = 10k, Rg = 100
VIN = 200mVP-P
TIME (s)
OUT
P
UT
(
V
)
IN
PUT
(
V
)
-0.26
-0.22
-0.18
-0.14
-0.10
-0.06
-0.02
0.02
0.06
0
20
40
60
80
100 120 140 160 180 200
-15
-13
-11
-9
-7
-5
-3
-1
1
INPUT
OUTPUT
VS = ±15V
RL = 10k
AV = 100
CL = 4pF
Rf = 10k, Rg = 100
VIN = 200mVP-P
CAPACITANCE (pF)
O
VERS
H
OOT
(%)
0
5
10
15
20
25
30
35
40
45
50
1
10
100
1,000
10,000
OV
ER
SH
OO
T -
VS = ±15V
RL = 10k
AV = 1
VOUT = 100mVP-P
OV
ER
SH
OO
T +
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