参数资料
| 型号： | ISL28210SOICEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 2/4页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL28210 8SOIC |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 每 IC 通道数： | 2 - 双 |
| 放大器类型： | J-FET |
| 输出类型： | 单端 |
| 转换速率： | 20 V/µs |
| 电流 - 输出 / 通道： | 50mA |
| 工作温度： | -40°C ~ 125°C |
| 电流供应（主 IC）： | 2.55mA |
| 电压 - 电源，单路/双路(±)： | 9 V ~ 40 V，±4.5 V ~ 20 V |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL28210 |
Application Note 1594
Amplifier Configuration (Figure 3)
The schematic of the op amp input stage with the
components supplied is shown in Figure 3, with a closed
loop gain of 10V/V. The differential amplifier gain is
The output (Figure 4) also has additional resistor and
capacitor placements for filtering and loading.
NOTE: Operational amplifiers are sensitive to output
capacitance and may oscillate. In the event of oscillation,
expressed in Equation 1:
V OUT = ( V IN+ – V IN- ) ? ( R F ? R IN ) + V REF
(EQ. 1)
reduce output capacitance by using shorter cables, or
add a resistor in series with the output.
For single-ended input with an inverting gain G = -10V/V,
the IN+ input is grounded and the signal is supplied to the
IN- input. VREF can be connected to a reference voltage
between the V+ and V- supply rails. For non-inverting
operation with G = 11V/V, the IN- input is grounded and
the signal is supplied to the IN+ input. The non-inverting
gain is strongly dependent on any resistance from IN- to
GND. For good gain accuracy, a 0 Ω resistor should be
installed on the empty R5 pad.
IN-A J1
IN+A J2
R1
DNP
R2
R4
0
R11
10k
R14
10k
C1
OPEN
R13
100k
FROM V OUTA
TO INA -
TO INA +
User-selectable Options
(Figures 3 and 4)
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier
inputs, the VREF input, outputs and the amplifier
DNP
R15 R18
DNP 100k
FIGURE 3. INPUT STAGE
VREF
feedback loops.
A voltage divider (Figure 3, R18 and R15) can be added
to establish a power supply-tracking common mode
reference using the VREF input. The inverting and non-
inverting inputs have additional resistor placements for
V OUT_A
R26
0
C6
OPEN
J15
OUT A
adding input attenuation, or to establish input DC offsets
through the VREF pin.
FIGURE 4. OUTPUT STAGE
TABLE 1. ISL28210SOICEVAL1Z COMPONENTS PARTS LIST
DEVICE #
C2, C4
C3, C5
C1, C6, C7, C8, C9, C10
D1
R11, R14, R21, R24
R13, R23
R1-R3, R5-R8, R10, R12,
R15, R17, R20, R22, R28-
R30, R32, R34-R36
U1 (ISL28210FBZ)
DESCRIPTION
CAP, SMD, 1206, 1μF, 50V, 10%, X7R, ROHS
CAP, SMD, 0603, 0.01μF, 50V, 10%, X7R, ROHS
CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS
40V DUAL SERIES SCHOTTKY BARRIER DIODE
RESISTOR, SMD, 0603, 10k Ω , 1%, 1/16W, ROHS
RESISTOR, SMD, 0603, 100k Ω , 1%, 1/16W, ROHS
RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS
ISL28210FBZ, IC PRECISION LOW NOSIE JFET OP AMP,
SOIC, ROHS
2
COMMENTS
Power Supply Decoupling
Power Supply Decoupling
User selectable capacitors - not populated
Reverse Power Protection
Gain Setting Resistor
Gain Setting Feedback Resistor
User selectable resistors - not populated
AN1594.0
October 1, 2010
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