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| 型号： | ISL29021IROZ-EVALZ |
| 厂商： | Intersil |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL29021IROZ |
| 标准包装： | 1 |
| 系列： | * |
ISL29021
of the interrupt. An unexpected camera flash, for example,
can be ignored by setting the persistency to 8 integration
cycles.
I 2 C Interface
There are eight 8-bit registers available inside the ISL29021.
The two command registers define the operation of the device.
The command registers do not change until the registers are
overwritten. The two 8-bit data Read Only registers are for the
ADC output and the Timer output. The data registers contain
the ADC's latest digital output, or the number of clock cycles in
the previous integration period. The four 8-bit interrupt registers
hold 16-bit interrupt high and low thresholds.
The ISL29021’s I 2 C interface slave address is internally hard-
wired as 1000100. When 1000100x with x as R or W is sent
after the Start condition, this device compares the first seven
bits of this byte to its address and matches.
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. The I 2 C bus master always drives
the SCL (clock) line, while either the master or the slave can
drive the SDA (data) line. Figure 2 shows a sample write.
Every I 2 C transaction begins with the master asserting a
start condition (SDA falling while SCL remains high). The
following byte is driven by the master, and includes the slave
address and read/write bit. The receiving device is
responsible for pulling SDA low during the
acknowledgement period. Every I 2 C transaction ends with
the master asserting a stop condition (SDA rising while SCL
remains high).
For more information about the I 2 C standard, please consult
the Philips ? I 2 C specification documents.
I 2 C DATA
START
DEVICE ADDRESS
W A
REGISTER ADDRESS
STOP START
DEVICE ADDRESS
A
DATA BYTE0
I 2 C SDA
IN
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W
A
SDA DRIVEN BY ISL29021
I 2 C SDA
OUT
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
I 2 C CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 1. I 2 C READ TIMING DIAGRAM SAMPLE
START
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
FUNCTIONS
A
STOP
I 2 C DATA
I 2 C SDA IN
A6 A5 A4 A3 A2 A1 A0
W
A
R7 R6 R5 R4 R3 R2 R1 R0
A
B7 B6 B5 B4 B3 B2 B1 B0
A
I 2 C SDA OUT
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
I 2 C CLK IN
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 2. I 2 C WRITE TIMING DIAGRAM SAMPLE
5
FN6732.0
March 3, 2009
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