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参数资料
| 型号： | ISL29027IROZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 4/13页 |
| 文件大小： | 0K |
| 描述： | IC SENSOR LIGHT-PROXIMITY 8ODFN |
| 标准包装： | 3,000 |
| 主体材料： | * |
| 电源电压： | 2.25 V ~ 3.63 V |
| 输出类型： | I²C? |
| 端子类型： | PC 引脚 |
| 封装/外壳： | 8-DFN |
ISL29027
Electrical Specifications
V DD = 3.0V, T A = +25°C, R EXT = 499k Ω 1% tolerance. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 9) TYP (Note 9) UNIT
PSRR IRDR
( Δ I IRDR )/( Δ V IRDR )
PROX_DR = 0; V IRDR = 0.5V to 4.3V
4
mA/V
NOTES:
7. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
8. Ability to guarantee I IRDR leakage of ~1nA is limited by test hardware. .
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
I 2 C Electrical Specifications
(Note 10).
For SCL and SDA unless otherwise noted, V DD = 3V, T A = +25°C, R EXT = 499k Ω 1% tolerance
PARAMETER
V I2C
DESCRIPTION
Supply Voltage Range for I 2 C Interface
CONDITION
MIN
1.7
TYP
MAX
3.63
UNIT
V
f SCL
V IL
V IH
V hys
V OL
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level Output Voltage (Open-drain) at 4mA Sink
Current
1.25
0.05V DD
400
0.55
0.4
kHz
V
V
V
V
I i
t SP
t AA
C i
Input Leakage for each SDA, SCL Pin
Pulse Width of Spikes that must be Suppressed by
the Input Filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL Pin
-10
10
50
900
10
μA
ns
ns
pF
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
t BUF
C b
R pull-up
t VD;DAT
t VD:ACK
V nL
V nH
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Capacitive Load for Each Bus Line
SDA and SCL System Bus Pull-up Resistor
Data Valid Time
Data Valid Acknowledge Time
Noise Margin at the LOW Level
Noise Margin at the HIGH Level
After this period, the first clock pulse is
generated
Measured at the 30% of VDD crossing
(Note 11)
(Note 11)
Maximum is determined by t R and t F
600
1300
600
600
30
100
20 + 0.1xC b
20 + 0.1xC b
600
1300
1
0.1VDD
0.2VDD
400
0.9
0.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k Ω
μs
μs
V
V
NOTES:
10. All parameters in I 2 C Electrical Specifications table are guaranteed by design and simulation.
11. Cb is the capacitance of the bus in pF.
4
FN7815.1
February 2, 2012
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