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| 型号： | ISL29029IROZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC SENSOR LIGHT-PROXIMITY 8ODFN |
| 标准包装： | 3,000 |
| 带接近传感器： | 是 |
| 波长： | 530nm |
| 电源电压： | * |
| 输出类型： | I²C? |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL29029
Electrical Specifications
V DD = 3.0V, T A = +25°C, R EXT = 499k Ω 1% tolerance. (Continued)
PARAMETER
I IRDR_0
I IRDR_1
IRDR Sink Current
IRDR Sink Current
DESCRIPTION
CONDITION
PROX_DR = 0; V IRDR = 0.5V
PROX_DR = 1; V IRDR = 0.5V
MIN
90
TYP
110
220
MAX
130
UNIT
mA
mA
I IRDR_LEAK
V IRDR
IRDR Leakage Current
Acceptable Voltage Range on IRDR Pin
PROX_EN = 0; V DD = 3.63V (Note 10)
Register bit PROX_DR = 0
0.5
0.001
1
4.3
μA
V
t PULSE
V REF
F I2C
Net I IRDR On Time Per PROX Reading
Voltage of R EXT Pin
I 2 C Clock Rate Range
100
0.51
400
μs
V
kHz
V I2C
Supply Voltage Range for I 2 C Interface
1.7
3.63
V
V IL
V IH
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
1.25
0.55
V
V
I SDA
I INT
PSRR IRDR
SDA Current Sinking Capability
INT Current Sinking Capability
( Δ I IRDR )/( Δ V IRDR )
V OL = 0.4V
V OL = 0.4V
PROX_DR = 0; V IRDR = 0.5V to 4.3V
3
3
5
5
4
mA
mA
mA/V
NOTES:
7. Nonlinearity is defined as: [(Measured Counts at 53 lux)-(Expected Counts at 53 lux)]/4095. Expected counts are calculated using an endpoint linear-
fit trendline from measurements at 0 lux and 90 lux.
8. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux
level.
9. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
10. Ability to guarantee I IRDR leakage of ~1nA is limited by test hardware.
11. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.
I2C Electrical Specifications For SCL and SDA unless otherwise noted, V DD = 3V, T A = +25°C, R EXT = 499k Ω 1% tolerance
(Note 12).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V I2C
Supply Voltage Range for
I 2 C
Interface
1.7
3.63
V
f SCL
V IL
V IH
V hys
V OL
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level output voltage (open-drain) at 4mA sink
current
1.25
0.05V DD
400
0.55
0.4
kHz
V
V
V
V
I i
t SP
t AA
C i
Input Leakage for each SDA, SCL pin
Pulse width of spikes that must be suppressed by
the input filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL pin
-10
10
50
900
10
μA
ns
ns
pF
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
After this period, the first clock pulse is
generated
Measured at the 30% of VDD crossing
600
1300
600
600
30
ns
ns
ns
ns
ns
4
FN7682.0
November 23, 2010
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