参数资料
| 型号： | ISL34340INZ |
| 厂商： | Intersil |
| 文件页数： | 9/10页 |
| 文件大小： | 0K |
| 描述： | IC LNG-RCH VID SERDES 64-EPTQFP |
| 标准包装： | 160 |
| 功能： | 串行器/解串器 |
| 输入类型： | LVCMOS |
| 输出类型： | LVCMOS |
| 输入数： | 2 |
| 输出数： | 2 |
| 电源电压： | 1.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TQFP 裸露焊盘 |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
8
FN6255.1
June 23, 2008
Applications
Overview
A pair of ISL34340 SERDES transports 24-bit parallel video
(16-bit parallel video for the ISL34320) along with auxiliary
data over a single 100
Ω differential cable either to a display
or from a camera. Auxiliary data is transferred in both
directions and can be used for remote configuration and
telemetry.
The benefits include lower EMI, lower costs, greater
reliability and space savings. The same device can be
configured to be either a serializer or deserializer by setting
one pin (VIDEO_TX), simplifying inventory. RGBA/B/C,
VSYNC, HSYNC, and DATAEN pins are inputs in serializer
mode and outputs in deserializer mode.
The video data presented to the serializer on the parallel
LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel
video at the remote end by the deserializer. The
side-channel data is transferred between the SERDES pair
during two lines of the vertical video blanking interval.
When the side-channel is enabled, there will be a number of
PCLK cycles uncertainty from frame-to-frame. This should
not cause sync problems with most displays, as this occurs
during the vertical front porch of the blanking period. When
properly configured, the SERDES link supports end-to-end
transport with fewer than one error in 1010 bits.
Differential Signals and Termination
The ISL34340 serializes the 24-bit parallel data at 30x the
PCLK_IN frequency. The ISL34320 serializes the 16-bit
parallel data at 20x the PCLK_IN frequency. The extra 2 bits
per word come from the 8b/10b encoding scheme.
The high bit rate of the differential serial data requires
special care in the layout of traces on PCBs, in the choice
and assembly of connectors, and in the cables themselves.
PCB traces need to be adjacent and matched in length (so
as to minimize the imbalanced coupling to other traces or
elements), and of a geometry to match the impedance of the
transmitter and receiver, to minimize reflections. Similar care
needs to be applied to the choice of connectors and cables.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines. External termination
cannot be used unless the side-channel is disabled.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode
voltage difference and local power supply variations
between two SERDES. The serializer outputs DC balanced
8b/10b line code, which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nF on
the serializer board and 27nF on the deserializer board. The
value of the AC-coupling capacitor is very critical since a
value too small will attenuate the high speed signal at low
clock rate. A value too big will slow down the turn around
time for the side-channel.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into
PCLK_IN pin. REF_CLK is used to recover the clock from
the high speed serial stream. REF_CLK is very sensitive to
any instability. The following conditions must be met at all
times after power is applied to the deserializer, or else the
deserializer may need a manual reset:
REF_CLK frequency must be within the limits specified
REF_CLK amplitude must be stable.
A simple 3.3V CMOS crystal oscillator can be used for
REF_CLK.
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all
times, including during power-up and power-down. To meet
FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
HSYNC
VSYNC
DATAEN
PCLK_OUT
RGB[A:C][7:0]
1/fOUT
TODC
TOR
TDV
TOF
VALID DATA
DATA HELD AT PREVIOUS VALUE
VALID DATA
TDV
VIDEO_TX = 0
ISL34340
相关PDF资料 |
PDF描述 |
|---|---|
| ISL34341INZ | IC VIDEO SERDES LONG 64-EPTQFP |
| ISL35111DRZ-TS | IC DE-EMP DRIVER SGL 16QFN |
| ISL35411DRZ-T7 | IC DVR QUAD 46QFN |
| ISL36111DRZ-TS | IC EQUALIZER REC 11.1GBPS 16QFN |
| ISL36411DRZ-TS | IC EQUALIZER REC 11.3GBPS 46QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL34340INZ-T13 | 功能描述:IC VIDEO SERDES LONG 64-EPTQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 串行器，解串行器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 功能:解串器 数据速率:2.5Gbps 输入类型:串行 输出类型:并联 输入数:- 输出数:24 电源电压:1.8 V ~ 3.3 V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:64-TQFP 裸露焊盘 供应商设备封装:64-TQFP-EP（10x10） 包装:管件 |
| ISL34340KIT1Z | 功能描述:EVALUATION BOARD FOR ISL34340 RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:* 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| ISL34341 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel |
| ISL34341INZ | 功能描述:串行器/解串器 - Serdes ISL34341INZ WSVGA 24-BIT LNG-REACH VID RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| ISL34341INZ-T13 | 功能描述:串行器/解串器 - Serdes ISL34341INZ DISPLAY SERDES W/MSTR MD OP RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
发布紧急采购，3分钟左右您将得到回复。