参数资料
型号: ISL35111DRZ-EVALZ
厂商: Intersil
文件页数: 4/9页
文件大小: 0K
描述: EVAL BAORD FOR ISL35111DRZ
标准包装: 1
系列: *
ISL35111
4
FN6975.2
July 19, 2012
Output Return Loss Limit
(Differential)
SDD22
100MHz to 4.1GHz
See 6
dB
4.1GHz to 11.1GHz
See 7
dB
Output Return Loss Limit
(Common Mode)
SCC22
100MHz to 2.5GHz
See 9
dB
2.5GHz to 11.1GHz
-3
dB
Residual Deterministic Jitter
11.1Gbps; no channel attenuation; de-emphasis
disabled
0.1
UI
Random Jitter
0.7
psRMS
Output Transition Time
tr, tf
20% to 80%
35
ps
Minimum De-Emphasis Level
0dB
Maximum De-Emphasis Level
4dB
De-Emphasis Resolution
0.5
dB
NOTES:
6. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*
√(f ), with f in GHz. Established by characterization and not production tested.
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3 + 13Log10(f/5.5), with f in GHz. Established by characterization and not
production tested.
8. Limits established by characterization and are not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not production tested.
10. Measured using a PRBS 215-1 pattern.
11. Rise and fall times measured using a 2GHz clock with a 20ps edge rate and with de-emphasis disabled.
12. Compliance to limits is assured by characterization and design.
Electrical Characteristics VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 12)
TYP
MAX
(Note 12) UNITS NOTES
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched into the chip
evaluation board. The ISL35111 output signal is then visualized on a scope to determine signal integrity parameters such as jitter.
FIGURE 2. DEVICE CHARACTERIZATION TEST SETUP
3A. DE-EMPHASIS 0
3B. DE-EMPHASIS 6
FIGURE 3. ISL35111 10.3125Gbps OUTPUT; NO CHANNEL; PRBS-31
P a tte r n
G ene r a to r
IS L 3 5 111 E v al
Bo a r d
O s c illo s c o p e
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