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参数资料
| 型号： | ISL3873IK |
| 厂商： | INTERSIL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Wireless LAN Integrated Medium Access Controller with Baseband Processor |
| 中文描述： | 1 CHANNEL(S), 11M bps, LOCAL AREA NETWORK CONTROLLER, PBGA192 |
| 封装： | 14 X 14 MM, PLASTIC, BGA-192 |
| 文件页数： | 8/31页 |
| 文件大小： | 215K |
| 代理商： | ISL3873IK |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
8
SYNTHCLK(PK1) Width Hi
t
H1
t
L1
t
CYC
/2 - 10
t
CYC
/2 - 10
-
t
CYC
/2 + 10
t
CYC
/2 + 10
ns
SYNTHCLK(PK1) Width Lo
-
ns
SERIAL PORT
SYNTHCLK(PK1) Clock Period
t
CYC
t
H1
, t
L1
t
CD
83ns
-
4000
ns
Low Width
t
CYC
/2 -10
-
-
t
CYC
/2 + 10
-
ns
Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD,
SYNTHDATA(PK2) Outputs
10
ns
Setup Time of SYTHNDATA(PK2) Read to SYTHNCLK(PK1) Falling Edge
t
DRS
t
DRH
t
DWH
15
-
-
ns
Hold Time of SYTHNDATA(PK2) Read from SYTHNCLK(PK1) Falling Edge
0
-
-
Hold Time of SYTHNDATA(PK2) Write from SYTHNCLK(PK1) Falling Edge
0
-
-
SYSTEM INTERFACE - PC CARD IO READ 16
Data Delay After HIORD-
t
DIORD
t
HIORD
t
WIORD
t
SUA
t
HA
t
SUCE
t
HCE
t
SUREG
t
HREG
t
DFINPACK
d
DRINPACK
t
DFWT
t
DRWT
t
WWT
-
-
100
ns
Data Hold Following HIORD-
0
-
-
ns
HIORD- Width Time
165
-
-
ns
Address Setup Before HIORD-
70
-
-
ns
Address Hold Following HIORD-
20
-
-
ns
HCE(1,2)- Setup Before HIORD-
5
-
-
ns
HCE(1,2)- Hold After HIORD-
20
-
-
ns
HREG- Setup Before HIORD-
5
-
-
ns
HREG- Hold Following HIORD-
0
-
-
ns
HINPACK- Delay Falling from HIORD-
0
-
45
ns
HINPACK- Delay Rising from HIORDN
30
-
45
ns
HWAIT-
-
-
35
ns
Data Delay from HWAIT- Rising
-
-
0
ns
HWAIT- Width Time
-
-
12,000
ns
SYSTEM INTERFACE - PC CARD IO WRITE 16
Data Setup Before HIOWR-
t
SUIOWR
t
HIOWR
t
WIOWR
t
SUA
t
HA
t
SUCE
t
HCE
t
SUREG
t
HREG
t
DFWT
t
WWT
t
DRIOWR
30
-
92
ns
Data Hold Following HIOWR-
20
-
-
ns
HIOWRN- Width Time
165
-
-
ns
Address Setup Before HIOWR-
70
-
-
ns
Address Hold Following HIOWR-
20
-
-
ns
HCE(1,2)- Setup Before HIOWR-
5
-
-
ns
HCE(1,2)- Hold Following HIOWR-
20
-
-
ns
HREG- Setup Before HIOWR-
5
-
-
ns
HREG- Hold Following HIOWR-
0
-
-
ns
HWAIT- Delay Falling from HIOWR-
-
-
35
ns
HWAIT- Width Time
-
-
12,000
ns
HIOWRN High from HWAIT- High
0
-
-
ns
BASEBAND SIGNALS
Full Scale Input Voltage (V
P-P
)
Input Bandwidth (-0.5dB)
0.25
0.50
1.0
V
-
20
-
MHz
Input Capacitance
-
5
-
pF
k
MHz
Input Impedance (DC)
5
-
-
FS (Sampling Frequency)
-
-
22
AC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
ISL3873
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL3873IK96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor |
| ISL3874 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
| ISL3874IK | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
| ISL3874IK96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
| ISL3880 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor |
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