参数资料
型号: ISL43841IRZ
厂商: Intersil
文件页数: 3/14页
文件大小: 0K
描述: IC MUX/DEMUX DUAL 4X1 20QFN
标准包装: 75
功能: 多路复用器/多路分解器
电路: 2 x 4:1
导通状态电阻: 45 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 2 V ~ 12 V,±2 V ~ 6 V
电流 - 电源: 1µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(4x4)
包装: 管件
11
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 9). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Power-Supply Considerations
The ISL43841 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL43841 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
This switch device performs equally well when operated with
bipolar or single voltage supplies.The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
Curves for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.7V
to 10V. At 12V the VIH level is about 3.3V. This is still below
the CMOS guaranteed high output minimum level of 4V, but
noise margin is reduced. For best results with a 12V supply,
use a logic family that provides a VOH greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50
systems, signal response is reasonably flat even past
100MHz (see Figures 16 and 17). Figures 16 and 17 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another.
Figure 18 details the high Off Isolation and Crosstalk
rejection provided by this family. At 10MHz, Off Isolation is
about 55dB in 50
systems, decreasing approximately 20dB
per decade as frequency increases. Higher load impedances
decrease Off Isolation and Crosstalk rejection due to the
voltage divider action of the switch OFF impedance and the
load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
FIGURE 9. INPUT OVERVOLTAGE PROTECTION
V-
VCOM
VNO
OPTIONAL PROTECTION
V+
LOGIC
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1k
ISL43841
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