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参数资料
| 型号： | ISL45042IR |
| 厂商： | INTERSIL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | LCD Module Calibrator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO8 |
| 封装： | 3 X 3 MM, PLASTIC, TDFN-8 |
| 文件页数： | 4/7页 |
| 文件大小： | 198K |
| 代理商： | ISL45042IR |
4
FN6072.3
June 21, 2005
Application Information
This device provides the ability to reduce the flicker of an
LCD panel by adjustment of the VCOM voltage during
production test and alignment. A 128-step resolution is
provided under digital control, which adjusts the sink current
of the output. The output is connected to an external voltage
divider, so that the device will have the capability to reduce
the voltage on the output by increasing the output sink
current.
The adjustment of the output and the programming of the
non-volatile memory are provided on one pin, while the
counter enable (CE) is provided on a separate pin. The
output is adjusted via the CTL pin either by counting up with
a mid to low transition, or by counting down with a mid to
high transition. Once the minimum or maximum value is
reached on the 128-steps, the device will not overflow or
underflow beyond that minimum or maximum value. An
increment of the counter will increase the output sink
current, which will lower the voltage on the external voltage
divider. A decrement of the counter will decrease the output
sink current, which will raise the voltage on the external
voltage divider.
Once the desired output level is obtained, the part can store
its setting using the non-volatile memory in the device. (See
the Non-volatile programming section for detailed
information.)
The output adjustment can also be prevented from changing
by pulling down the counter enable pin.
CTL EEPROM Programming
Signal Time
CTL
PT
>4.9V
Full
200
-
-
μ
s
Programming Time
P
T
Full
100
ms
EE Write Cycles
EE
WC
Guaranteed by Design
25
1000
-
-
Cycles
SET Voltage Resolution
SET
VR
(Note 4)
Full
7
-
-
Bits
SET Differential Nonlinearity
SET
DN
Monotonic Over Temperature
Full
-
-
±
1
LSB
SET Zero-Scale Error
SET
ZSE
Full
-
-
±
2
LSB
SET Full-Scale Error
SET
FSE
Full
-
-
±
8
LSB
SET Current
ISET
Through R
SET
(Note 5)
Full
-
-
120
μ
A
SET External Resistance
SET
ER
To GND, AVDD = 20V (Note 5)
Full
10
-
200
k
To GND, AVDD = 4.5V (Note 5)
Full
2.25
-
45
k
AVDD to SET Voltage Attenuation
AVDD to
SET
Full
-
1:20
-
V/V
OUT Settling Time
OUT
ST
to
±
0.5 LSB Error Band (Note 5)
Full
-
20
-
μ
s
OUT Voltage Range
V
OUT
(Note 5)
Full
VSET +
0.5V
-
13
V
OUT Voltage Drift
OUT
VD
(Note 5)
25 to 55
-
-
10
mV
NOTES:
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AVDD = 20V.
4. The Counter value is set to mid-scale
±
4 LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9k
; Unless Otherwise Specified.
Typicals are at T
A
= 25°C
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
R
SET
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
-
+
ISL45042
SET
OUT
AVDD
R
1
R
2
AVDD
ISL45042
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