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参数资料
| 型号： | ISL51002-EVALZ |
| 厂商： | Intersil |
| 文件页数： | 5/33页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL51002 |
| 标准包装： | 1 |
| 系列： | * |
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13
FN6164.3
February 29, 2012
0x04
Interrupt Status,
Write a 1 to each bit to clear
it, 0xFF to clear all.
0
CH0 Sync Changed
0: No change
1: CH0 activity or polarity changed
1
CH1 Sync Changed
0: No change
1: CH1 activity or polarity changed
2
CH2 Sync Changed
0: No change
1: CH2 activity or polarity changed
7
Reserved
Ignore this bit
4
Selected Input Channel
Disrupted
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
signal has changed (fast notification of a mode change)
5
Selected Input Channel
Changed
0: No change
1: Currently selected Input Channel’s HSYNC or VSYNC
period or pulse width has settled to a new value and can be
measured
6
VSYNC INT
0: Default state
1: VSYNC occurred
7
PADJ INT
0: Default state
1: Phase Adjustment function completed.
0x05
Interrupt Mask Register,
(0xFF)
0
CH0 Mask
0: Generate interrupt if CH0 sync activity, polarity, period, or
pulse width changes
1: Mask CH0 interrupt
1
CH1 Mask
0: Generate interrupt if CH1 sync activity, polarity, period, or
pulse width changes
1: Mask CH1 interrupt
2
CH2 Mask
0: Generate interrupt if CH2 sync activity, polarity, period, or
pulse width changes
1: Mask CH2 interrupt
3
Reserved
Set this bit to 1.
4
Input Disrupted Mask
0: Generate interrupt if selected Input Channel’s sync inputs
are disrupted
1: Mask Input Channel interrupt
5
Input Changed Mask
0: Generate interrupt after selected Input Channel period or
pulse width settles to new value
1: Mask Input Channel interrupt
6
VSYNC INT Mask
0: Generate interrupt every VSYNC
1: Mask VSYNC Interrupt
7
PADJ INT Mask
0: Generate interrupt upon phase adjustment block request
completion
1: Mask Phase adjustment interrupt
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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