参数资料
| 型号： | ISL5314IN |
| 厂商： | Intersil |
| 文件页数： | 2/17页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER DIGITAL 48-MQFP |
| 标准包装： | 250 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 125MHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 3 V ~ 5.5 V，4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
10
FN4901.3
January 19, 2010
Address Setup Time, tAS
Between ADDR and WR (Note 6)
12
--
ns
Address Hold Time, tAH
Between ADDR and WR (Note 6)
0
--
ns
UPDATE Pulse Width, tUW
(Note 6)
5
--
ns
UPDATE Setup Time, tUS
Between UPDATE and CLK (Note 6)
1
--
ns
UPDATE Hold Time, tUH
Between UPDATE and CLK (Note 6)
3
--
ns
UPDATE Latency, tUL
After UPDATE, before analog output change, if asserted after
writing to the control registers
-14
-
Clock
Cycles
UPDATE Latency, tUL
After UPDATE, before analog output change, if asserted before
writing to the control registers
-11
-
Clock
Cycles
Maximum PH Rate
Rate of PH1 and PH0 pins (Note 6)
fCLK/2
--
Hz
Phase Pulse Width, tPW
PH(1:0) (Note 6)
5
--
ns
Phase Setup Time, tPS
Between PH(1:0) change and CLK (Note 6)
1
--
ns
Phase Hold Time, tPH
Between PH(1:0) change and CLK (Note 6)
3
--
ns
Phase Latency, tPL
Between PH(1:0) change and analog output change
-
12
-
Clock
Cycles
Maximum ENOFR Rate
Rate of ENOFR (Note 6)
fCLK/2
--
Hz
ENOFR Pulse Width, tEW
ENOFR (Note 6)
5
--
ns
ENOFR Setup Time, tES
Between ENOFR and CLK (Note 6)
1
--
ns
ENOFR Hold Time, tEH
Between ENOFR and CLK (Note 6)
3
--
ns
ENOFR Latency, tEL
After ENOFR, before analog output change
-
14
-
Clock
Cycles
Write Enable Pulse Width, tWR
WE (Note 6)
5
--
ns
Write Enable Setup Time, tWS
Between WE and WR (Note 6)
2
--
ns
Write Enable Hold Time, tWH
Between WE and WR (Note 6)
4
--
ns
RESET Pulse Width, tRW
RESET (Note 6)
5
--
ns
RESET Setup Time, tRS
Between RESET and CLK
1
--
ns
RESET Latency to Output, tRL
After RESET, before analog output reflects reset values
-
11
-
Clock
Cycles
RESET Latency to Write, tRE
After RESET, before the control registers can be written to
-
1
-
Clock
Cycles
Maximum SCLK Rate
50
--
MSPS
SCLK Pulse Width, tSCW
5
--
ns
SDATA Pulse Width, tSDW
5
--
ns
SDATA Setup Time, tSDS
6
--
ns
SDATA Hold Time, tSDH
1
--
ns
SSYNC Pulse Width, tSSW
5
--
ns
SSYNC Setup Time, tSSS
6
--
ns
SSYNC Hold Time, tSSH
1
--
ns
COMPARATOR CHARACTERISTICS
Input Capacitance
-4
-
pF
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = -40°C to +85°C for
all Min and Max Values. TA = +25°C for All Typical Values. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
ISL5314
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