参数资料
型号: ISL54061EVAL1Z
厂商: Intersil
文件页数: 6/15页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL54061
标准包装: 1
主要目的: 接口,模拟开关
嵌入式:
已用 IC / 零件: ISL54061
主要属性: 2 x SPST 模拟开关
次要属性: 1.8 V ~ 6.5 V 电源
已供物品:
14
FN6580.2
November 3, 2009
ISL54060, ISL54061
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
0.10
0.08
SIDE VIEW
0.10
2X
E
A
B
C
0.10
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
8
7
D2
B
A
C
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
L1
9 L
M
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.70
0.75
0.80
-
A1
-
0.05
-
A3
0.20 REF
-
b
0.20
0.25
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
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