参数资料
型号: ISL54410EVAL1Z
厂商: Intersil
文件页数: 4/13页
文件大小: 0K
描述: EVAL BOARD 1 FOR ISL54410
标准包装: 1
系列: *
12
FN6983.1
January 14, 2010
ISL54409, ISL54410
Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 9/09
Nd and Ne refer to the number of terminals on D (4) and E (6) side,
Dimension b applies to the metallized terminal and is measured
The configuration of the pin #1 identifier is optional, but must be
All dimensions are in millimeters. Tolerances ±0.05mm unless
N is the number of terminals. Total 10 leads.
6.
3.
5.
4.
2.
Dimensioning and tolerancing conform to ASME Y14.5-1994.
1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
6
B
1.40
A
1.80
0.10 C
2X
INDEX AREA
0.10 C
2X
2
1
2
1
0.50
NX 0.40
5
7
PIN #1 ID
(DATUM A)
(DATUM B)
0.10 M C A B
0.05 M C
NX 0.20
10X
5
0.40 BSC
C
0.05 C
0.5
0.10 C
0.05 MAX
SEATING PLANE
NX (0.20)
SECTION "C-C"
e
CC
5
CL
TERMINAL TIP
(0.05 MAX)
0.40
0.127 REF
0.40
0.40 BSC
0.50
0.20
0.40
1.80
0.40
0.20
2.20
1.00
0.60
1.00
LAND PATTERN
10
respectively.
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Maximum package warpage is 0.05mm.
7.
Maximum allowable burrs is 0.076mm in all directions.
8.
JEDEC Reference MO-255.
9.
For additional information, to assist with the PCB Land Pattern
10.
Design effort, see Intersil Technical Brief TB389.
otherwise noted. Angles are in degrees.
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