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参数资料
| 型号： | ISL55291IUZ-T13 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 运动控制电子 |
| 英文描述： | Single and Dual Ultra-Low Noise, Ultra-Low Distortion, Rail-to-Rail, Low Power Op Amp |
| 中文描述： | DUAL OP-AMP, 800 uV OFFSET-MAX, 800 MHz BAND WIDTH, PDSO10 |
| 封装： | ROHS COMPLIANT, MSOP-10 |
| 文件页数： | 14/18页 |
| 文件大小： | 886K |
| 代理商： | ISL55291IUZ-T13 |
14
FN6263.1
March 30, 2007
Applications Information
Product Description
The ISL55191 and ISL55291 are voltage feedback
operational amplifiers designed for communication and
imaging applications requiring very low voltage and current
noise. Both parts features low distortion while drawing
moderately low supply current. The ISL55191 and ISL55291
use a classical voltage-feedback topology which allows them
to be used in a variety of applications where current-
feedback amplifiers are not appropriate because of
restrictions placed upon the feedback element used with the
amplifier.
Enable/Power-Down
Both devices can be operated from a single supply with a
voltage range of +3V to +5V, or from split ±1.5V to ±2.5V.
The logic level input to the ENABLE pins are TTL compatible
and are referenced to the -V terminal in both single and split
supply applications. The following discussion assumes
single supply operation.
The ISL55191 uses a logic “0” (<0.8V) to disable the
amplifier and the ISL55291 uses a logic “1” (>2V) to disable
its amplifiers. In this condition, the output(s) will be in a high
impedance state and the amplifier(s) current will be reduced
to 21μA. The ISL55191 has an internal pull-up on the EN pin
and is enabled by either floating or tying the EN pin to a
voltage >2V. The ISL55291 has internal pull-downs on the
EN pins and are enabled by either floating or tying the EN
pins to a voltage <0.8V. The enable pins should be tied
directly to their respective supply pins when not being used
(EN tied to -V for the ISL55291 and EN tied to +V for the
ISL55191).
Current Limiting
The ISL55191 and ISL55291 have no internal current-
limiting circuitry. If the output is shorted, it is possible to
exceed the Absolute Maximum Rating for output current or
power dissipation, potentially resulting in the destruction of
the device.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (T
JMAX
) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related as follows:
where:
P
DMAXTOTAL
is the sum of the maximum power
dissipation of each amplifier in the package (PD
MAX
)
PD
MAX
for each amplifier can be calculated as follows:
where:
T
MAX
= Maximum ambient temperature
θ
JA
= Thermal resistance of the package
PD
MAX
= Maximum power dissipation of 1 amplifier
V
S
= Supply voltage
I
MAX
= Maximum supply current of 1 amplifier
V
OUTMAX
= Maximum output voltage swing of the
application
R
L
= Load resistance
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Low
impedance ground plane construction is essential. Surface
mount components are recommended, but if leaded
components are used, lead lengths should be as short as
possible. The power supply pins must be well bypassed to
reduce the risk of oscillation. The combination of a 4.7μF
tantalum capacitor in parallel with a 0.01μF capacitor has
been shown to work well when placed at each supply pin.
For good AC performance, parasitic capacitance should be
kept to a minimum, especially at the inverting input. When
ground plane construction is used, it should be removed
from the area near the inverting input to minimize any stray
capacitance at that node. Carbon or Metal-Film resistors are
acceptable with the Metal-Film resistors giving slightly less
peaking and bandwidth because of additional series
inductance. Use of sockets (particularly for the SOIC
package) should be avoided if possible. Sockets add
parasitic inductance and capacitance which will result in
additional peaking and overshoot.
For inverting gains, this parasitic capacitance has little effect
because the inverting input is a virtual ground, but for non-
inverting gains, this capacitance (in conjunction with the
feedback and gain resistors) creates a pole in the feedback
path of the amplifier. This pole, if low enough in frequency,
has the same destabilizing effect as a zero in the forward
open-loop response. The use of large-value feedback and
gain resistors exacerbates the problem by further lowering
the pole frequency (increasing the possibility of oscillation.).
T
JMAX
T
MAX
θ
JA
xPD
MAXTOTAL
(
)
+
=
(EQ. 1)
PD
MAX
2*V
S
I
SMAX
V
S
(
- V
OUTMAX
)
V
L
----------------------------
×
+
×
=
(EQ. 2)
ISL55191, ISL55291
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