参数资料
型号: ISL5629IN
厂商: Intersil
文件页数: 3/12页
文件大小: 0K
描述: IC DAC DUAL 8BIT 3.3V 48-LQFP
标准包装: 250
位数: 8
数据接口: 并联
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 274mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
输出数目和类型: 4 电流,单极
采样率(每秒): 130M
11
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 8.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
RDIFF
ISL5629
RLOAD
FIGURE 6. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
1:1
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
FIGURE 7. ALTERNATIVE OUTPUT LOADING
ISL5629
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
RLOAD
RDIFF
RA
RB
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
Timing Diagram
FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
IOUT
50%
tPW1
tPW2
tSU
tHLD
tSU
tPD
tHLD
D7-D0
W0
W1
W2
W3
OUTPUT=W0
OUTPUT=W1
tPD
OUTPUT=W-1
ISL5629
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