参数资料
| 型号： | ISL5827INZ |
| 厂商： | Intersil |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT 3.3V 48-LQFP |
| 标准包装： | 250 |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 275 mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 260M |
5
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Resistance (Typical, Note 1)
θJA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
PARAMETER
TEST CONDITIONS
TA = -40°C TO 85°C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
12
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-1.25
±0.5
+1.25
LSB
Differential Linearity Error, DNL
(Note 8)
-1
±0.5
+1
LSB
Offset Error, IOS
IOUTA (Note 8)
-0.006
+0.006
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-3
±0.5
+3
% FSR
With Internal Reference (Notes 2, 8)
-3
±0.5
+3
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±50
-
ppm
FSR/°C
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/°C
Crosstalk
fCLK = 100MSPS, fOUT = 10MHz
-
83
-
dB
fCLK = 100MSPS, fOUT = 40MHz
-
74
-
dB
fCLK = 260MSPS, fOUT = 40.4MHz
-
73
-
dB
Gain Matching Between Channels
(DC Measurement)
As a percentage of Full Scale Range
-1.6
0.6
+1.6
% FSR
In dB Full Scale Range
-0.14
0.05
+0.14
dB FSR
Full Scale Output Current, IFS
220
22
mA
Output Voltage Compliance Range
(Note 3)
-1.0
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
260
300
-
MHz
Output Rise Time
Full Scale Step
-
1
-
ns
Output Fall Time
Full Scale Step
-
1
-
ns
Output Capacitance
-5
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√Hz
IOUTFS = 2mA
-
30
-
pA/
√Hz
ISL5827
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