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参数资料
| 型号： | ISL5829IN |
| 厂商： | Intersil |
| 文件页数： | 12/13页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT 3.3V 48-MQFP |
| 标准包装： | 250 |
| 功能： | D/A 转换器 |
| 频率： | 130MHz |
| RF 型： | GSM，EDGE，CDMA2000，WCMDA，TDS-CDMA |
| 次要属性： | 双路 12 位 |
| 封装/外壳： | 48-LQFP |
ISL5829
R A =R B =50 ? , R DIFF =100 ? , assuming R LOAD =50 ? . The
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
R EQ = 0.5 x (R LOAD // R DIFF // R A ), WHERE R A =R B
AT EACH OUTPUT
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
OUTA
R A
V OUT = (2 x OUTA x R EQ )V
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
ISL5829
OUTB
R DIFF
R B
R LOAD
R EQ = 0.5 x (R LOAD // R DIFF )
AT EACH OUTPUT
V OUT = (2 x OUTA x R EQ )V
R LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
OUTA
R DIFF
1:1
R LOAD
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Propagation Delay
ISL5829
OUTB
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
R LOAD REPRESENTS THE
L OAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
Timing Diagram
CLK
t PW1
t PW2
50%
t SU
t HLD
t SU
t HLD
t SU
t HLD
D11-D0
W 0
W 1
W 2
W 3
t PD
t PD
OUTPUT=W 0
I OUT
OUTPUT=W -1
OUTPUT=W 1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
12
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