参数资料
| 型号： | ISL59834IRZ |
| 厂商： | Intersil |
| 文件页数： | 6/17页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO FILTER CHRG PUMP 44-QFN |
| 标准包装： | 43 |
| 应用： | 滤波器 |
| 电路数： | 4 |
| -3db带宽： | 9MHz |
| 电流 - 电源： | 28mA |
| 电流 - 输出 / 通道： | 50mA |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-VFQFN 裸露焊盘 |
| 供应商设备封装： | 44-QFN-EP（7x7） |
| 包装： | 管件 |
| 产品目录页面： | 1247 (CN2011-ZH PDF) |
14
FN6268.1
June 11, 2008
clock pins for both charge pumps (CLKA and CLKB) must be
shorted together.
To reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
VEEOUT Pins
VEEAOUT and VEEBOUT are the output pins for the charge
pumps. Keep in mind that these outputs are fully regulated
supplies that must be properly bypassed. Bypass these pins
with a 0.47F ceramic capacitor placed as close to the pin
and connected to the ground plane of the board.
VEEIN Pins
VEEAIN and VEEBIN are the subtrate connections for the
ISL59834, these two pins must be shorted together. To
reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
Video Performance
DIFFERENTIAL GAIN/PHASE
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency and phase response as DC levels are changed at
the output. Special circuitry has been incorporated into the
ISL59834 to reduce the output impedance variation with the
current output. This results in outstanding differential gain
and differential phase specifications of 0.45% and 0.15°,
while driving 150
Ω at a gain of +2V/V.
NTSC
The ISL59834, generating a negative rail internally, is ideally
suited for NTSC video with its accompanying negative-going
sync signals.
S-VIDEO
For a typical S-video application with two S-video signals,
connect the luma signals to Channel 1 and 3, and connect
the chrominance signals to Channel 2 and 4. For clamp
timing, connect SYNC_OUTA to SYNC_INA and
SYNC_OUTB to SYNC_INB. See the “S-Video Typical
Application Circuit” on page 8.
YPbPr
For a typical component video application, connect Y to
Channel 1, Pb to Channel 2 and Pr to Channel 4. Channel 3
can be optionally used a composite signal. For the clamp
timing, connect SYNC_OUTA to both SYNC_INA and
SYNC_INB and leave SYNC_OUTB floating. See the
“YPbPr Typical Application Circuit” on page 7.
AC-Coupled Inputs
SYNC TIP CLAMP (CHANNEL 1 AND 3)
The ISL59834 features a sync tip clamp that forces the black
level of the output video signal to ground. This ensures that
the sync-tip voltage level will be approximately -300mV at
the back-termination resistor of a standard video load. The
clamp is activated whenever the input voltage falls below 0V.
The correction voltage required to do this is stored across
the input AC-coupling capacitor. Refer to Typical Application
Circuit for a detailed diagram.
KEYED CLAMP (CHANNEL 2 AND 4)
Channel 2 and Channel 4 have a keyed clamp, which forces
the output to ground when SYNC_INA (Channel 2) or
SYNC_INB (Channel 4) are driven to the logic high state.
The SYNC_IN pins may be connected to either SYNC_OUT
pins or they may be driven by external sources.
SYNC DETECTOR AND CLAMP TIMING
Channel 1 and Channel 3 also have sync detectors whose
outputs are available at SYNC_OUTA and SYNC_OUTB
pins respectively.
The slice level for the sync detectors is between 100mV to
200mV. This means that if the signal level is below 100mV at
Channel 1 or 3, then SYNC_OUTA or SYNC_OUTB are
high. If the signal level is above 200mV, then SYNC_OUTA
or SYNC_OUTB are low. Figure 29 shows the operation of
the sync detector.
DC-Coupled Inputs (Channel 1 and 3)
When DC-coupling the inputs, ensure that the lowest signal
level is greater than +50mV to prevent the clamp from
turning on and distorting the output. When DC-coupled, the
ISL59834 shifts the signal by -620mV.
Amplifier Disable
The ISL59834 can be disabled and its output placed in a
high impedance state. ENABLEA shuts off Channel 1 and 2
while ENABLEB shuts off Channel 3 and 4. Both ENABLE
pins must be shorted together. The turn-off time is around
10ns and the turn-on time is around 35s. The turn-on time
+300mV
+0mV
NTSC LUMINANCE
CHANNEL 1 OR 3
INPUT
+1.00V
100mV < VSLICE < 200mV
+0mV
+3.3V
SYNC_OUTA OR
SYNC_OUTB
FIGURE 29. SYNC DETECTOR SLICE LEVEL
ISL59834
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相关代理商/技术参数 |
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| ISL59837 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:200MHz Single Supply Video Driver With Charge Pump and Power Down |
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| ISL59837IAZ-EVALZ | 功能描述:EVAL BOARD FOR ISL59837IAZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| ISL59837IAZ-T7 | 功能描述:IC VIDEO DRIVER TRUE SGL 16-QSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
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